arch/sh/kernel/cpu/sh4a/perf_event.c

Source file repositories/reference/linux-study-clean/arch/sh/kernel/cpu/sh4a/perf_event.c

File Facts

System
Linux kernel
Corpus path
arch/sh/kernel/cpu/sh4a/perf_event.c
Extension
.c
Size
7637 bytes
Lines
300
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Performance events support for SH-4A performance counters
 *
 *  Copyright (C) 2009, 2010  Paul Mundt
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/perf_event.h>
#include <asm/processor.h>

#define PPC_CCBR(idx)	(0xff200800 + (sizeof(u32) * idx))
#define PPC_PMCTR(idx)	(0xfc100000 + (sizeof(u32) * idx))

#define CCBR_CIT_MASK	(0x7ff << 6)
#define CCBR_DUC	(1 << 3)
#define CCBR_CMDS	(1 << 1)
#define CCBR_PPCE	(1 << 0)

#ifdef CONFIG_CPU_SHX3
/*
 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
 * and PMCTR locations remains tentatively constant. This change remains
 * wholly undocumented, and was simply found through trial and error.
 *
 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
 * it's unclear when this ceased to be the case. For now we always use
 * the new location (if future parts keep up with this trend then
 * scanning for them at runtime also remains a viable option.)
 *
 * The gap in the register space also suggests that there are other
 * undocumented counters, so this will need to be revisited at a later
 * point in time.
 */
#define PPC_PMCAT	0xfc100240
#else
#define PPC_PMCAT	0xfc100080
#endif

#define PMCAT_OVF3	(1 << 27)
#define PMCAT_CNN3	(1 << 26)
#define PMCAT_CLR3	(1 << 25)
#define PMCAT_OVF2	(1 << 19)
#define PMCAT_CLR2	(1 << 17)
#define PMCAT_OVF1	(1 << 11)
#define PMCAT_CNN1	(1 << 10)
#define PMCAT_CLR1	(1 << 9)
#define PMCAT_OVF0	(1 << 3)
#define PMCAT_CLR0	(1 << 1)

static struct sh_pmu sh4a_pmu;

/*
 * Supported raw event codes:
 *
 *	Event Code	Description
 *	----------	-----------
 *
 *	0x0000		number of elapsed cycles
 *	0x0200		number of elapsed cycles in privileged mode
 *	0x0280		number of elapsed cycles while SR.BL is asserted
 *	0x0202		instruction execution
 *	0x0203		instruction execution in parallel
 *	0x0204		number of unconditional branches
 *	0x0208		number of exceptions
 *	0x0209		number of interrupts
 *	0x0220		UTLB miss caused by instruction fetch
 *	0x0222		UTLB miss caused by operand access
 *	0x02a0		number of ITLB misses
 *	0x0028		number of accesses to instruction memories
 *	0x0029		number of accesses to instruction cache
 *	0x002a		instruction cache miss
 *	0x022e		number of access to instruction X/Y memory
 *	0x0030		number of reads to operand memories
 *	0x0038		number of writes to operand memories
 *	0x0031		number of operand cache read accesses
 *	0x0039		number of operand cache write accesses
 *	0x0032		operand cache read miss
 *	0x003a		operand cache write miss
 *	0x0236		number of reads to operand X/Y memory
 *	0x023e		number of writes to operand X/Y memory
 *	0x0237		number of reads to operand U memory
 *	0x023f		number of writes to operand U memory
 *	0x0337		number of U memory read buffer misses
 *	0x02b4		number of wait cycles due to operand read access
 *	0x02bc		number of wait cycles due to operand write access
 *	0x0033		number of wait cycles due to operand cache read miss
 *	0x003b		number of wait cycles due to operand cache write miss

Annotation

Implementation Notes