arch/sh/kernel/cpu/sh4a/setup-sh7757.c
Source file repositories/reference/linux-study-clean/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
File Facts
- System
- Linux kernel
- Corpus path
arch/sh/kernel/cpu/sh4a/setup-sh7757.c- Extension
.c- Size
- 34329 bytes
- Lines
- 1246
- Domain
- Architecture Layer
- Bucket
- arch/sh
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/platform_device.hlinux/init.hlinux/serial.hlinux/serial_sci.hlinux/io.hlinux/mm.hlinux/dma-mapping.hlinux/sh_timer.hlinux/sh_dma.hlinux/sh_intc.hlinux/usb/ohci_pdriver.hcpu/dma-register.hcpu/sh7757.hasm/mmzone.hasm/platform_early.h
Detected Declarations
function sh7757_devices_setupfunction plat_early_device_setupfunction plat_irq_setupfunction plat_irq_setup_pinsfunction plat_mem_setup
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* SH7757 Setup
*
* Copyright (C) 2009, 2011 Renesas Solutions Corp.
*
* based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/sh_timer.h>
#include <linux/sh_dma.h>
#include <linux/sh_intc.h>
#include <linux/usb/ohci_pdriver.h>
#include <cpu/dma-register.h>
#include <cpu/sh7757.h>
#include <asm/mmzone.h>
#include <asm/platform_early.h>
static struct plat_sci_port scif2_platform_data = {
.scscr = SCSCR_REIE,
.type = PORT_SCIF,
};
static struct resource scif2_resources[] = {
DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
DEFINE_RES_IRQ(evt2irq(0x700)),
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 0,
.resource = scif2_resources,
.num_resources = ARRAY_SIZE(scif2_resources),
.dev = {
.platform_data = &scif2_platform_data,
},
};
static struct plat_sci_port scif3_platform_data = {
.scscr = SCSCR_REIE,
.type = PORT_SCIF,
};
static struct resource scif3_resources[] = {
DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
DEFINE_RES_IRQ(evt2irq(0xb80)),
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 1,
.resource = scif3_resources,
.num_resources = ARRAY_SIZE(scif3_resources),
.dev = {
.platform_data = &scif3_platform_data,
},
};
static struct plat_sci_port scif4_platform_data = {
.scscr = SCSCR_REIE,
.type = PORT_SCIF,
};
static struct resource scif4_resources[] = {
DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
DEFINE_RES_IRQ(evt2irq(0xf00)),
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 2,
.resource = scif4_resources,
.num_resources = ARRAY_SIZE(scif4_resources),
.dev = {
.platform_data = &scif4_platform_data,
},
};
static struct sh_timer_config tmu0_platform_data = {
.channels_mask = 3,
};
Annotation
- Immediate include surface: `linux/platform_device.h`, `linux/init.h`, `linux/serial.h`, `linux/serial_sci.h`, `linux/io.h`, `linux/mm.h`, `linux/dma-mapping.h`, `linux/sh_timer.h`.
- Detected declarations: `function sh7757_devices_setup`, `function plat_early_device_setup`, `function plat_irq_setup`, `function plat_irq_setup_pins`, `function plat_mem_setup`.
- Atlas domain: Architecture Layer / arch/sh.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.