arch/sparc/include/asm/chmctrl.h

File Facts

System

Linux kernel

Corpus path

arch/sparc/include/asm/chmctrl.h

Extension

.h

Size

8096 bytes

Lines

185

Domain

Architecture Layer

Bucket

arch/sparc

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _SPARC64_CHMCTRL_H
#define _SPARC64_CHMCTRL_H

/* Cheetah memory controller programmable registers. */
#define CHMCTRL_TCTRL1		0x00 /* Memory Timing Control I		*/
#define CHMCTRL_TCTRL2		0x08 /* Memory Timing Control II	*/
#define CHMCTRL_TCTRL3		0x38 /* Memory Timing Control III	*/
#define CHMCTRL_TCTRL4		0x40 /* Memory Timing Control IV	*/
#define CHMCTRL_DECODE1		0x10 /* Memory Address Decode I		*/
#define CHMCTRL_DECODE2		0x18 /* Memory Address Decode II	*/
#define CHMCTRL_DECODE3		0x20 /* Memory Address Decode III	*/
#define CHMCTRL_DECODE4		0x28 /* Memory Address Decode IV	*/
#define CHMCTRL_MACTRL		0x30 /* Memory Address Control		*/

/* Memory Timing Control I */
#define TCTRL1_SDRAMCTL_DLY	0xf000000000000000UL
#define TCTRL1_SDRAMCTL_DLY_SHIFT     60
#define TCTRL1_SDRAMCLK_DLY	0x0e00000000000000UL
#define TCTRL1_SDRAMCLK_DLY_SHIFT     57
#define TCTRL1_R		0x0100000000000000UL
#define TCTRL1_R_SHIFT 		      56
#define TCTRL1_AUTORFR_CYCLE	0x00fe000000000000UL
#define TCTRL1_AUTORFR_CYCLE_SHIFT    49
#define TCTRL1_RD_WAIT		0x0001f00000000000UL
#define TCTRL1_RD_WAIT_SHIFT	      44
#define TCTRL1_PC_CYCLE		0x00000fc000000000UL
#define TCTRL1_PC_CYCLE_SHIFT	      38
#define TCTRL1_WR_MORE_RAS_PW	0x0000003f00000000UL
#define TCTRL1_WR_MORE_RAS_PW_SHIFT   32
#define TCTRL1_RD_MORE_RAW_PW	0x00000000fc000000UL
#define TCTRL1_RD_MORE_RAS_PW_SHIFT   26
#define TCTRL1_ACT_WR_DLY	0x0000000003f00000UL
#define TCTRL1_ACT_WR_DLY_SHIFT	      20
#define TCTRL1_ACT_RD_DLY	0x00000000000fc000UL
#define TCTRL1_ACT_RD_DLY_SHIFT	      14
#define TCTRL1_BANK_PRESENT	0x0000000000003000UL
#define TCTRL1_BANK_PRESENT_SHIFT     12
#define TCTRL1_RFR_INT		0x0000000000000ff8UL
#define TCTRL1_RFR_INT_SHIFT	      3
#define TCTRL1_SET_MODE_REG	0x0000000000000004UL
#define TCTRL1_SET_MODE_REG_SHIFT     2
#define TCTRL1_RFR_ENABLE	0x0000000000000002UL
#define TCTRL1_RFR_ENABLE_SHIFT	      1
#define TCTRL1_PRECHG_ALL	0x0000000000000001UL
#define TCTRL1_PRECHG_ALL_SHIFT	      0

/* Memory Timing Control II */
#define TCTRL2_WR_MSEL_DLY	0xfc00000000000000UL
#define TCTRL2_WR_MSEL_DLY_SHIFT      58
#define TCTRL2_RD_MSEL_DLY	0x03f0000000000000UL
#define TCTRL2_RD_MSEL_DLY_SHIFT      52
#define TCTRL2_WRDATA_THLD	0x000c000000000000UL
#define TCTRL2_WRDATA_THLD_SHIFT      50
#define TCTRL2_RDWR_RD_TI_DLY	0x0003f00000000000UL
#define TCTRL2_RDWR_RD_TI_DLY_SHIFT   44
#define TCTRL2_AUTOPRECHG_ENBL	0x0000080000000000UL
#define TCTRL2_AUTOPRECHG_ENBL_SHIFT  43
#define TCTRL2_RDWR_PI_MORE_DLY	0x000007c000000000UL
#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
#define TCTRL2_RDWR_1_DLY	0x0000003f00000000UL
#define TCTRL2_RDWR_1_DLY_SHIFT       32
#define TCTRL2_WRWR_PI_MORE_DLY	0x00000000f8000000UL
#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
#define TCTRL2_WRWR_1_DLY	0x0000000007e00000UL
#define TCTRL2_WRWR_1_DLY_SHIFT       21
#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
#define TCTRL2_R		0x0000000000008000UL
#define TCTRL2_R_SHIFT		      15
#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0

/* Memory Timing Control III */
#define TCTRL3_SDRAM_CTL_DLY	0xf000000000000000UL
#define TCTRL3_SDRAM_CTL_DLY_SHIFT    60
#define TCTRL3_SDRAM_CLK_DLY	0x0e00000000000000UL
#define TCTRL3_SDRAM_CLK_DLY_SHIFT    57
#define TCTRL3_R		0x0100000000000000UL
#define TCTRL3_R_SHIFT		      56
#define TCTRL3_AUTO_RFR_CYCLE	0x00fe000000000000UL
#define TCTRL3_AUTO_RFR_CYCLE_SHIFT   49
#define TCTRL3_RD_WAIT		0x0001f00000000000UL
#define TCTRL3_RD_WAIT_SHIFT	      44
#define TCTRL3_PC_CYCLE		0x00000fc000000000UL
#define TCTRL3_PC_CYCLE_SHIFT	      38
#define TCTRL3_WR_MORE_RAW_PW	0x0000003f00000000UL
#define TCTRL3_WR_MORE_RAW_PW_SHIFT   32
#define TCTRL3_RD_MORE_RAW_PW	0x00000000fc000000UL
#define TCTRL3_RD_MORE_RAW_PW_SHIFT   26
#define TCTRL3_ACT_WR_DLY	0x0000000003f00000UL

Annotation

• Atlas domain: Architecture Layer / arch/sparc.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.