arch/sparc/include/asm/hypervisor.h
Source file repositories/reference/linux-study-clean/arch/sparc/include/asm/hypervisor.h
File Facts
- System
- Linux kernel
- Corpus path
arch/sparc/include/asm/hypervisor.h- Extension
.h- Size
- 117692 bytes
- Lines
- 3528
- Domain
- Architecture Layer
- Bucket
- arch/sparc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct hv_tsb_descrstruct hv_fault_statusstruct hv_trap_trace_controlstruct hv_trap_trace_entrystruct ldc_mtable_entrystruct hv_mmu_statisticsstruct hv_ncs_queue_entrystruct hv_ncs_qconf_argstruct hv_ncs_qtail_update_arg
Annotated Snippet
struct hv_tsb_descr {
unsigned short pgsz_idx;
unsigned short assoc;
unsigned int num_ttes; /* in TTEs */
unsigned int ctx_idx;
unsigned int pgsz_mask;
unsigned long tsb_base;
unsigned long resv;
};
#endif
#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
#define HV_TSB_DESCR_ASSOC_OFFSET 0x02
#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
#define HV_TSB_DESCR_RESV_OFFSET 0x18
/* Page size bitmask. */
#define HV_PGSZ_MASK_8K (1 << 0)
#define HV_PGSZ_MASK_64K (1 << 1)
#define HV_PGSZ_MASK_512K (1 << 2)
#define HV_PGSZ_MASK_4MB (1 << 3)
#define HV_PGSZ_MASK_32MB (1 << 4)
#define HV_PGSZ_MASK_256MB (1 << 5)
#define HV_PGSZ_MASK_2GB (1 << 6)
#define HV_PGSZ_MASK_16GB (1 << 7)
/* Page size index. The value given in the TSB descriptor must correspond
* to the smallest page size specified in the pgsz_mask page size bitmask.
*/
#define HV_PGSZ_IDX_8K 0
#define HV_PGSZ_IDX_64K 1
#define HV_PGSZ_IDX_512K 2
#define HV_PGSZ_IDX_4MB 3
#define HV_PGSZ_IDX_32MB 4
#define HV_PGSZ_IDX_256MB 5
#define HV_PGSZ_IDX_2GB 6
#define HV_PGSZ_IDX_16GB 7
/* MMU fault status area.
*
* MMU related faults have their status and fault address information
* placed into a memory region made available by privileged code. Each
* virtual processor must make a mmu_fault_area_conf() call to tell the
* hypervisor where that processor's fault status should be stored.
*
* The fault status block is a multiple of 64-bytes and must be aligned
* on a 64-byte boundary.
*/
#ifndef __ASSEMBLER__
struct hv_fault_status {
unsigned long i_fault_type;
unsigned long i_fault_addr;
unsigned long i_fault_ctx;
unsigned long i_reserved[5];
unsigned long d_fault_type;
unsigned long d_fault_addr;
unsigned long d_fault_ctx;
unsigned long d_reserved[5];
};
#endif
#define HV_FAULT_I_TYPE_OFFSET 0x00
#define HV_FAULT_I_ADDR_OFFSET 0x08
#define HV_FAULT_I_CTX_OFFSET 0x10
#define HV_FAULT_D_TYPE_OFFSET 0x40
#define HV_FAULT_D_ADDR_OFFSET 0x48
#define HV_FAULT_D_CTX_OFFSET 0x50
#define HV_FAULT_TYPE_FAST_MISS 1
#define HV_FAULT_TYPE_FAST_PROT 2
#define HV_FAULT_TYPE_MMU_MISS 3
#define HV_FAULT_TYPE_INV_RA 4
#define HV_FAULT_TYPE_PRIV_VIOL 5
#define HV_FAULT_TYPE_PROT_VIOL 6
#define HV_FAULT_TYPE_NFO 7
#define HV_FAULT_TYPE_NFO_SEFF 8
#define HV_FAULT_TYPE_INV_VA 9
#define HV_FAULT_TYPE_INV_ASI 10
#define HV_FAULT_TYPE_NC_ATOMIC 11
#define HV_FAULT_TYPE_PRIV_ACT 12
#define HV_FAULT_TYPE_RESV1 13
#define HV_FAULT_TYPE_UNALIGNED 14
#define HV_FAULT_TYPE_INV_PGSZ 15
#define HV_FAULT_TYPE_MCD 17
#define HV_FAULT_TYPE_MCD_DIS 18
/* Values 16 --> -2 are reserved. */
#define HV_FAULT_TYPE_MULTIPLE -1
/* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
Annotation
- Detected declarations: `struct hv_tsb_descr`, `struct hv_fault_status`, `struct hv_trap_trace_control`, `struct hv_trap_trace_entry`, `struct ldc_mtable_entry`, `struct hv_mmu_statistics`, `struct hv_ncs_queue_entry`, `struct hv_ncs_qconf_arg`, `struct hv_ncs_qtail_update_arg`.
- Atlas domain: Architecture Layer / arch/sparc.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.