arch/sparc/kernel/iommu.c
Source file repositories/reference/linux-study-clean/arch/sparc/kernel/iommu.c
File Facts
- System
- Linux kernel
- Corpus path
arch/sparc/kernel/iommu.c- Extension
.c- Size
- 19492 bytes
- Lines
- 777
- Domain
- Architecture Layer
- Bucket
- arch/sparc
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/export.hlinux/slab.hlinux/delay.hlinux/device.hlinux/dma-map-ops.hlinux/errno.hlinux/iommu-helper.hlinux/bitmap.hasm/iommu-common.hlinux/pci.hasm/iommu.hiommu_common.hkernel.h
Detected Declarations
function __volatile__function iopte_make_dummyfunction iommu_table_initfunction iommu_alloc_ctxfunction iommu_free_ctxfunction dma_4u_free_coherentfunction dma_4u_map_physfunction strbuf_flushfunction dma_4u_unmap_physfunction dma_4u_map_sgfunction fetch_sg_ctxfunction dma_4u_unmap_sgfunction dma_4u_sync_single_for_cpufunction dma_4u_sync_sg_for_cpufunction dma_4u_supportedexport dma_ops
Annotated Snippet
if (unlikely(n == lowest)) {
printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
n = 0;
}
}
if (n)
__set_bit(n, iommu->ctx_bitmap);
return n;
}
static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
{
if (likely(ctx)) {
__clear_bit(ctx, iommu->ctx_bitmap);
if (ctx < iommu->ctx_lowest_free)
iommu->ctx_lowest_free = ctx;
}
}
static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_addrp, gfp_t gfp,
unsigned long attrs)
{
unsigned long order, first_page;
struct iommu *iommu;
struct page *page;
int npages, nid;
iopte_t *iopte;
void *ret;
size = IO_PAGE_ALIGN(size);
order = get_order(size);
if (order >= 10)
return NULL;
nid = dev->archdata.numa_node;
page = alloc_pages_node(nid, gfp, order);
if (unlikely(!page))
return NULL;
first_page = (unsigned long) page_address(page);
memset((char *)first_page, 0, PAGE_SIZE << order);
iommu = dev->archdata.iommu;
iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
if (unlikely(iopte == NULL)) {
free_pages(first_page, order);
return NULL;
}
*dma_addrp = (iommu->tbl.table_map_base +
((iopte - iommu->page_table) << IO_PAGE_SHIFT));
ret = (void *) first_page;
npages = size >> IO_PAGE_SHIFT;
first_page = __pa(first_page);
while (npages--) {
iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
IOPTE_WRITE |
(first_page & IOPTE_PAGE));
iopte++;
first_page += IO_PAGE_SIZE;
}
return ret;
}
static void dma_4u_free_coherent(struct device *dev, size_t size,
void *cpu, dma_addr_t dvma,
unsigned long attrs)
{
struct iommu *iommu;
unsigned long order, npages;
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
iommu = dev->archdata.iommu;
iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
order = get_order(size);
if (order < 10)
free_pages((unsigned long)cpu, order);
}
static dma_addr_t dma_4u_map_phys(struct device *dev, phys_addr_t phys,
size_t sz, enum dma_data_direction direction,
unsigned long attrs)
{
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/export.h`, `linux/slab.h`, `linux/delay.h`, `linux/device.h`, `linux/dma-map-ops.h`, `linux/errno.h`, `linux/iommu-helper.h`.
- Detected declarations: `function __volatile__`, `function iopte_make_dummy`, `function iommu_table_init`, `function iommu_alloc_ctx`, `function iommu_free_ctx`, `function dma_4u_free_coherent`, `function dma_4u_map_phys`, `function strbuf_flush`, `function dma_4u_unmap_phys`, `function dma_4u_map_sg`.
- Atlas domain: Architecture Layer / arch/sparc.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.