arch/sparc/kernel/tsb.S

Source file repositories/reference/linux-study-clean/arch/sparc/kernel/tsb.S

File Facts

System
Linux kernel
Corpus path
arch/sparc/kernel/tsb.S
Extension
.S
Size
13575 bytes
Lines
592
Domain
Architecture Layer
Bucket
arch/sparc
Inferred role
Architecture Layer: arch/sparc
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <asm/tsb.h>
#include <asm/hypervisor.h>
#include <asm/page.h>
#include <asm/cpudata.h>
#include <asm/mmu.h>

	.text
	.align	32

	/* Invoked from TLB miss handler, we are in the
	 * MMU global registers and they are setup like
	 * this:
	 *
	 * %g1: TSB entry pointer
	 * %g2:	available temporary
	 * %g3:	FAULT_CODE_{D,I}TLB
	 * %g4:	available temporary
	 * %g5:	available temporary
	 * %g6: TAG TARGET
	 * %g7:	available temporary, will be loaded by us with
	 *      the physical address base of the linux page
	 *      tables for the current address space
	 */
tsb_miss_dtlb:
	mov		TLB_TAG_ACCESS, %g4
	ldxa		[%g4] ASI_DMMU, %g4
	srlx		%g4, PAGE_SHIFT, %g4
	ba,pt		%xcc, tsb_miss_page_table_walk
	 sllx		%g4, PAGE_SHIFT, %g4

tsb_miss_itlb:
	mov		TLB_TAG_ACCESS, %g4
	ldxa		[%g4] ASI_IMMU, %g4
	srlx		%g4, PAGE_SHIFT, %g4
	ba,pt		%xcc, tsb_miss_page_table_walk
	 sllx		%g4, PAGE_SHIFT, %g4

	/* At this point we have:
	 * %g1 --	PAGE_SIZE TSB entry address
	 * %g3 --	FAULT_CODE_{D,I}TLB
	 * %g4 --	missing virtual address
	 * %g6 --	TAG TARGET (vaddr >> 22)
	 */
tsb_miss_page_table_walk:
	TRAP_LOAD_TRAP_BLOCK(%g7, %g5)

	/* Before committing to a full page table walk,
	 * check the huge page TSB.
	 */
#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)

661:	ldx		[%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
	nop
	.section	.sun4v_2insn_patch, "ax"
	.word		661b
	mov		SCRATCHPAD_UTSBREG2, %g5
	ldxa		[%g5] ASI_SCRATCHPAD, %g5
	.previous

	cmp		%g5, -1
	be,pt		%xcc, 80f
	 nop

	/* We need an aligned pair of registers containing 2 values
	 * which can be easily rematerialized.  %g6 and %g7 foot the
	 * bill just nicely.  We'll save %g6 away into %g2 for the
	 * huge page TSB TAG comparison.
	 *
	 * Perform a huge page TSB lookup.
	 */

Annotation

Implementation Notes