arch/sparc/lib/clear_page.S

Source file repositories/reference/linux-study-clean/arch/sparc/lib/clear_page.S

File Facts

System
Linux kernel
Corpus path
arch/sparc/lib/clear_page.S
Extension
.S
Size
2565 bytes
Lines
108
Domain
Architecture Layer
Bucket
arch/sparc
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/export.h>
#include <linux/pgtable.h>
#include <asm/visasm.h>
#include <asm/thread_info.h>
#include <asm/page.h>
#include <asm/spitfire.h>
#include <asm/head.h>

	/* What we used to do was lock a TLB entry into a specific
	 * TLB slot, clear the page with interrupts disabled, then
	 * restore the original TLB entry.  This was great for
	 * disturbing the TLB as little as possible, but it meant
	 * we had to keep interrupts disabled for a long time.
	 *
	 * Now, we simply use the normal TLB loading mechanism,
	 * and this makes the cpu choose a slot all by itself.
	 * Then we do a normal TLB flush on exit.  We need only
	 * disable preemption during the clear.
	 */

	.text

	.globl		_clear_page
	EXPORT_SYMBOL(_clear_page)
_clear_page:		/* %o0=dest */
	ba,pt		%xcc, clear_page_common
	 clr		%o4

	/* This thing is pretty important, it shows up
	 * on the profiles via do_anonymous_page().
	 */
	.align		32
	.globl		clear_user_page
	EXPORT_SYMBOL(clear_user_page)
clear_user_page:	/* %o0=dest, %o1=vaddr */
	lduw		[%g6 + TI_PRE_COUNT], %o2
	sethi		%hi(PAGE_OFFSET), %g2
	sethi		%hi(PAGE_SIZE), %o4

	ldx		[%g2 + %lo(PAGE_OFFSET)], %g2
	sethi		%hi(PAGE_KERNEL_LOCKED), %g3

	ldx		[%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
	sub		%o0, %g2, %g1		! paddr

	and		%o1, %o4, %o0		! vaddr D-cache alias bit

	or		%g1, %g3, %g1		! TTE data
	sethi		%hi(TLBTEMP_BASE), %o3

	add		%o2, 1, %o4
	add		%o0, %o3, %o0		! TTE vaddr

	/* Disable preemption.  */
	mov		TLB_TAG_ACCESS, %g3
	stw		%o4, [%g6 + TI_PRE_COUNT]

	/* Load TLB entry.  */
	rdpr		%pstate, %o4
	wrpr		%o4, PSTATE_IE, %pstate
	stxa		%o0, [%g3] ASI_DMMU
	stxa		%g1, [%g0] ASI_DTLB_DATA_IN
	sethi		%hi(KERNBASE), %g1
	flush		%g1
	wrpr		%o4, 0x0, %pstate

	mov		1, %o4

clear_page_common:
	VISEntryHalf

Annotation

Implementation Notes