arch/x86/events/intel/uncore_snbep.c
Source file repositories/reference/linux-study-clean/arch/x86/events/intel/uncore_snbep.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/events/intel/uncore_snbep.c- Extension
.c- Size
- 208164 bytes
- Lines
- 6995
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/cpu_device_id.hasm/msr.huncore.huncore_discovery.h
Detected Declarations
enum perf_uncore_iio_freerunning_type_idenum perf_uncore_snr_iio_freerunning_type_idenum perf_uncore_snr_imc_freerunning_type_idenum perf_uncore_icx_iio_freerunning_type_idenum perf_uncore_icx_imc_freerunning_type_idenum perf_uncore_spr_iio_freerunning_type_idenum perf_uncore_spr_imc_freerunning_type_idenum perf_uncore_dmr_iio_freerunning_type_idfunction snbep_uncore_pci_disable_boxfunction snbep_uncore_pci_enable_boxfunction snbep_uncore_pci_enable_eventfunction snbep_uncore_pci_disable_eventfunction snbep_uncore_pci_read_counterfunction snbep_uncore_pci_init_boxfunction snbep_uncore_msr_disable_boxfunction snbep_uncore_msr_enable_boxfunction snbep_uncore_msr_enable_eventfunction snbep_uncore_msr_disable_eventfunction snbep_uncore_msr_init_boxfunction snbep_cbox_put_constraintfunction __snbep_cbox_get_constraintfunction snbep_cbox_filter_maskfunction snbep_cbox_get_constraintfunction snbep_cbox_hw_configfunction snbep_pcu_alter_erfunction snbep_pcu_get_constraintfunction snbep_pcu_put_constraintfunction snbep_pcu_hw_configfunction snbep_uncore_cpu_initfunction snbep_qpi_hw_configfunction snbep_qpi_enable_eventfunction upi_nodeid_groupidfunction topology_gidnid_mapfunction snbep_pci2phy_map_initfunction list_for_each_entryfunction snbep_uncore_pci_initfunction ivbep_uncore_msr_init_boxfunction ivbep_uncore_pci_init_boxfunction ivbep_cbox_filter_maskfunction ivbep_cbox_get_constraintfunction ivbep_cbox_hw_configfunction ivbep_cbox_enable_eventfunction ivbep_uncore_cpu_initfunction ivbep_uncore_irp_enable_eventfunction ivbep_uncore_irp_disable_eventfunction ivbep_uncore_irp_read_counterfunction ivbep_uncore_pci_initfunction knl_cha_filter_mask
Annotated Snippet
static struct pci_driver snbep_uncore_pci_driver = {
.name = "snbep_uncore",
.id_table = snbep_uncore_pci_ids,
};
#define NODE_ID_MASK 0x7
/* Each three bits from 0 to 23 of GIDNIDMAP register correspond Node ID. */
#define GIDNIDMAP(config, id) (((config) >> (3 * (id))) & 0x7)
static int upi_nodeid_groupid(struct pci_dev *ubox_dev, int nodeid_loc, int idmap_loc,
int *nodeid, int *groupid)
{
int ret;
/* get the Node ID of the local register */
ret = pci_read_config_dword(ubox_dev, nodeid_loc, nodeid);
if (ret)
goto err;
*nodeid = *nodeid & NODE_ID_MASK;
/* get the Node ID mapping */
ret = pci_read_config_dword(ubox_dev, idmap_loc, groupid);
if (ret)
goto err;
err:
return ret;
}
static int topology_gidnid_map(int nodeid, u32 gidnid)
{
int i, die_id = -1;
/*
* every three bits in the Node ID mapping register maps
* to a particular node.
*/
for (i = 0; i < 8; i++) {
if (nodeid == GIDNIDMAP(gidnid, i)) {
if (topology_max_dies_per_package() > 1)
die_id = i;
else
die_id = topology_phys_to_logical_pkg(i);
if (die_id < 0)
die_id = -ENODEV;
break;
}
}
return die_id;
}
/*
* build pci bus to socket mapping
*/
static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool reverse)
{
struct pci_dev *ubox_dev = NULL;
int i, bus, nodeid, segment, die_id;
struct pci2phy_map *map;
int err = 0;
u32 config = 0;
while (1) {
/* find the UBOX device */
ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
if (!ubox_dev)
break;
bus = ubox_dev->bus->number;
/*
* The nodeid and idmap registers only contain enough
* information to handle 8 nodes. On systems with more
* than 8 nodes, we need to rely on NUMA information,
* filled in from BIOS supplied information, to determine
* the topology.
*/
if (nr_node_ids <= 8) {
err = upi_nodeid_groupid(ubox_dev, nodeid_loc, idmap_loc,
&nodeid, &config);
if (err)
break;
segment = pci_domain_nr(ubox_dev->bus);
raw_spin_lock(&pci2phy_map_lock);
map = __find_pci2phy_map(segment);
if (!map) {
raw_spin_unlock(&pci2phy_map_lock);
err = -ENOMEM;
break;
}
Annotation
- Immediate include surface: `asm/cpu_device_id.h`, `asm/msr.h`, `uncore.h`, `uncore_discovery.h`.
- Detected declarations: `enum perf_uncore_iio_freerunning_type_id`, `enum perf_uncore_snr_iio_freerunning_type_id`, `enum perf_uncore_snr_imc_freerunning_type_id`, `enum perf_uncore_icx_iio_freerunning_type_id`, `enum perf_uncore_icx_imc_freerunning_type_id`, `enum perf_uncore_spr_iio_freerunning_type_id`, `enum perf_uncore_spr_imc_freerunning_type_id`, `enum perf_uncore_dmr_iio_freerunning_type_id`, `function snbep_uncore_pci_disable_box`, `function snbep_uncore_pci_enable_box`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.