arch/x86/events/perf_event.h
Source file repositories/reference/linux-study-clean/arch/x86/events/perf_event.h
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/events/perf_event.h- Extension
.h- Size
- 51919 bytes
- Lines
- 1917
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/perf_event.hasm/fpu/xstate.hasm/intel_ds.hasm/cpu.hasm/msr.hperf_event_flags.h
Detected Declarations
struct event_constraintstruct amd_nbstruct er_accountstruct intel_shared_regsstruct intel_excl_statesstruct intel_excl_cntrsstruct x86_perf_task_contextstruct cpu_hw_eventsstruct extra_regstruct x86_pmu_quirkstruct arch_pebs_capstruct x86_hybrid_pmustruct x86_pmustruct x86_perf_task_context_optstruct x86_perf_task_contextstruct x86_perf_task_context_arch_lbrstruct x86_perf_task_context_arch_lbr_xsaveenum extra_reg_typeenum intel_excl_state_typeenum hybrid_pmu_typefunction constraint_matchfunction is_topdown_countfunction is_metric_eventfunction is_slots_eventfunction is_topdown_eventfunction check_leader_groupfunction is_branch_counters_groupfunction is_pebs_counter_event_groupfunction is_acr_event_groupfunction is_acr_self_reload_eventfunction x86_pmu_has_lbr_callstackfunction intel_pmu_topdown_event_updatefunction x86_pmu_config_addrfunction x86_pmu_event_addrfunction x86_pmu_fixed_ctr_addrfunction x86_pmu_rdpmc_indexfunction has_amd_brsfunction is_counter_pairfunction __x86_pmu_enable_eventfunction x86_pmu_disable_eventfunction x86_pmu_num_countersfunction x86_pmu_max_num_countersfunction x86_pmu_num_counters_fixedfunction x86_pmu_max_num_counters_fixedfunction x86_pmu_get_event_configfunction x86_pmu_has_rdpmc_user_disablefunction kernel_ipfunction address
Annotated Snippet
struct event_constraint {
union {
unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
u64 idxmsk64;
};
u64 code;
u64 cmask;
int weight;
int overlap;
int flags;
unsigned int size;
};
static inline bool constraint_match(struct event_constraint *c, u64 ecode)
{
return ((ecode & c->cmask) - c->code) <= (u64)c->size;
}
#define PERF_ARCH(name, val) \
PERF_X86_EVENT_##name = val,
/*
* struct hw_perf_event.flags flags
*/
enum {
#include "perf_event_flags.h"
};
#undef PERF_ARCH
#define PERF_ARCH(name, val) \
static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \
PERF_X86_EVENT_##name);
#include "perf_event_flags.h"
#undef PERF_ARCH
static inline bool is_topdown_count(struct perf_event *event)
{
return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
}
static inline bool is_metric_event(struct perf_event *event)
{
u64 config = event->attr.config;
return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
}
static inline bool is_slots_event(struct perf_event *event)
{
return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
}
static inline bool is_topdown_event(struct perf_event *event)
{
return is_metric_event(event) || is_slots_event(event);
}
int is_x86_event(struct perf_event *event);
static inline bool check_leader_group(struct perf_event *leader, int flags)
{
return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false;
}
static inline bool is_branch_counters_group(struct perf_event *event)
{
return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS);
}
static inline bool is_pebs_counter_event_group(struct perf_event *event)
{
return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
}
static inline bool is_acr_event_group(struct perf_event *event)
{
return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
}
static inline bool is_acr_self_reload_event(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
if (hwc->idx < 0)
return false;
Annotation
- Immediate include surface: `linux/perf_event.h`, `asm/fpu/xstate.h`, `asm/intel_ds.h`, `asm/cpu.h`, `asm/msr.h`, `perf_event_flags.h`.
- Detected declarations: `struct event_constraint`, `struct amd_nb`, `struct er_account`, `struct intel_shared_regs`, `struct intel_excl_states`, `struct intel_excl_cntrs`, `struct x86_perf_task_context`, `struct cpu_hw_events`, `struct extra_reg`, `struct x86_pmu_quirk`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.