arch/x86/include/asm/cpuid/leaf_types.h

Source file repositories/reference/linux-study-clean/arch/x86/include/asm/cpuid/leaf_types.h

File Facts

System: Linux kernel
Corpus path: arch/x86/include/asm/cpuid/leaf_types.h
Extension: .h
Size: 80481 bytes
Lines: 2351
Domain: Architecture Layer
Bucket: arch/x86
Inferred role: Architecture Layer: implementation source
Status: source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/types.h

Detected Declarations

struct leaf_0x0_0
struct leaf_0x1_0
struct leaf_0x2_0
struct leaf_0x4_n
struct leaf_0x5_0
struct leaf_0x6_0
struct leaf_0x7_0
struct leaf_0x7_1
struct leaf_0x7_2
struct leaf_0x9_0
struct leaf_0xa_0
struct leaf_0xb_n
struct leaf_0xd_0
struct leaf_0xd_1
struct leaf_0xd_n
struct leaf_0xf_0
struct leaf_0xf_1
struct leaf_0x10_0
struct leaf_0x10_n
struct leaf_0x10_3
struct leaf_0x12_0
struct leaf_0x12_1
struct leaf_0x12_n
struct leaf_0x14_0
struct leaf_0x14_1
struct leaf_0x15_0
struct leaf_0x16_0
struct leaf_0x17_0
struct leaf_0x17_n
struct leaf_0x18_n
struct leaf_0x19_0
struct leaf_0x1a_0
struct leaf_0x1b_n
struct leaf_0x1c_0
struct leaf_0x1d_0
struct leaf_0x1d_1
struct leaf_0x1e_0
struct leaf_0x1f_n
struct leaf_0x20_0
struct leaf_0x21_0
struct leaf_0x23_0
struct leaf_0x23_1
struct leaf_0x23_2
struct leaf_0x23_3
struct leaf_0x23_4
struct leaf_0x23_5
struct leaf_0x40000000_0
struct leaf_0x4c780001_0

Annotated Snippet

struct leaf_0x0_0 {
	// eax
	u32	max_std_leaf			: 32; // Highest standard CPUID leaf
	// ebx
	u32	cpu_vendorid_0			: 32; // CPU vendor ID string bytes 0 - 3
	// ecx
	u32	cpu_vendorid_2			: 32; // CPU vendor ID string bytes 8 - 11
	// edx
	u32	cpu_vendorid_1			: 32; // CPU vendor ID string bytes 4 - 7
};

/*
 * Leaf 0x1
 * CPU FMS (Family/Model/Stepping) + standard feature flags
 */

struct leaf_0x1_0 {
	// eax
	u32	stepping			:  4, // Stepping ID
		base_model			:  4, // Base CPU model ID
		base_family_id			:  4, // Base CPU family ID
		cpu_type			:  2, // CPU type
						:  2, // Reserved
		ext_model			:  4, // Extended CPU model ID
		ext_family			:  8, // Extended CPU family ID
						:  4; // Reserved
	// ebx
	u32	brand_id			:  8, // Brand index
		clflush_size			:  8, // CLFLUSH instruction cache line size
		n_logical_cpu			:  8, // Logical CPU count
		local_apic_id			:  8; // Initial local APIC physical ID
	// ecx
	u32	sse3				:  1, // Streaming SIMD Extensions 3 (SSE3)
		pclmulqdq			:  1, // PCLMULQDQ instruction support
		dtes64				:  1, // 64-bit DS save area
		monitor				:  1, // MONITOR/MWAIT support
		dscpl				:  1, // CPL Qualified Debug Store
		vmx				:  1, // Virtual Machine Extensions
		smx				:  1, // Safer Mode Extensions
		est				:  1, // Enhanced Intel SpeedStep
		tm2				:  1, // Thermal Monitor 2
		ssse3				:  1, // Supplemental SSE3
		cntxt_id			:  1, // L1 Context ID
		sdbg				:  1, // Silicon Debug
		fma				:  1, // FMA extensions using YMM state
		cx16				:  1, // CMPXCHG16B instruction support
		xtpr_update			:  1, // xTPR Update Control
		pdcm				:  1, // Perfmon and Debug Capability
						:  1, // Reserved
		pcid				:  1, // Process-context identifiers
		dca				:  1, // Direct Cache Access
		sse4_1				:  1, // SSE4.1
		sse4_2				:  1, // SSE4.2
		x2apic				:  1, // X2APIC support
		movbe				:  1, // MOVBE instruction support
		popcnt				:  1, // POPCNT instruction support
		tsc_deadline_timer		:  1, // APIC timer one-shot operation
		aes				:  1, // AES instructions
		xsave				:  1, // XSAVE (and related instructions) support
		osxsave				:  1, // XSAVE (and related instructions) are enabled by OS
		avx				:  1, // AVX instructions support
		f16c				:  1, // Half-precision floating-point conversion support
		rdrand				:  1, // RDRAND instruction support
		guest_status			:  1; // System is running as guest; (para-)virtualized system
	// edx
	u32	fpu				:  1, // Floating-Point Unit on-chip (x87)
		vme				:  1, // Virtual-8086 Mode Extensions
		de				:  1, // Debugging Extensions
		pse				:  1, // Page Size Extension
		tsc				:  1, // Time Stamp Counter
		msr				:  1, // Model-Specific Registers (RDMSR and WRMSR support)
		pae				:  1, // Physical Address Extensions
		mce				:  1, // Machine Check Exception
		cx8				:  1, // CMPXCHG8B instruction
		apic				:  1, // APIC on-chip
						:  1, // Reserved
		sep				:  1, // SYSENTER, SYSEXIT, and associated MSRs
		mtrr				:  1, // Memory Type Range Registers
		pge				:  1, // Page Global Extensions
		mca				:  1, // Machine Check Architecture
		cmov				:  1, // Conditional Move Instruction
		pat				:  1, // Page Attribute Table
		pse36				:  1, // Page Size Extension (36-bit)
		psn				:  1, // Processor Serial Number
		clflush				:  1, // CLFLUSH instruction
						:  1, // Reserved
		ds				:  1, // Debug Store
		acpi				:  1, // Thermal monitor and clock control
		mmx				:  1, // MMX instructions
		fxsr				:  1, // FXSAVE and FXRSTOR instructions

Annotation

Immediate include surface: `linux/types.h`.
Detected declarations: `struct leaf_0x0_0`, `struct leaf_0x1_0`, `struct leaf_0x2_0`, `struct leaf_0x4_n`, `struct leaf_0x5_0`, `struct leaf_0x6_0`, `struct leaf_0x7_0`, `struct leaf_0x7_1`, `struct leaf_0x7_2`, `struct leaf_0x9_0`.
Atlas domain: Architecture Layer / arch/x86.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.