arch/x86/include/asm/cpuid/types.h
Source file repositories/reference/linux-study-clean/arch/x86/include/asm/cpuid/types.h
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/include/asm/cpuid/types.h- Extension
.h- Size
- 5671 bytes
- Lines
- 226
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/build_bug.hlinux/types.hasm/cpuid/leaf_types.h
Detected Declarations
struct cpuid_regsstruct leaf_0x2_regstruct leaf_0x2_tablestruct leaf_parse_infostruct cpuid_leavesstruct cpuid_tableenum cpuid_regs_idxenum _cache_table_typeenum _tlb_table_type
Annotated Snippet
struct cpuid_regs {
u32 eax;
u32 ebx;
u32 ecx;
u32 edx;
};
enum cpuid_regs_idx {
CPUID_EAX = 0,
CPUID_EBX,
CPUID_ECX,
CPUID_EDX,
};
#define CPUID_LEAF_MWAIT 0x05
#define CPUID_LEAF_DCA 0x09
#define CPUID_LEAF_XSTATE 0x0d
#define CPUID_LEAF_TSC 0x15
#define CPUID_LEAF_FREQ 0x16
#define CPUID_LEAF_TILE 0x1d
#define CPUID_RANGE(idx) ((idx) & 0xffff0000)
#define CPUID_RANGE_MAX(idx) (CPUID_RANGE(idx) + 0xffff)
#define CPUID_BASE_START 0x00000000
#define CPUID_BASE_END CPUID_RANGE_MAX(CPUID_BASE_START)
/*
* Types for CPUID(0x2) parsing:
*/
struct leaf_0x2_reg {
u32 : 31,
invalid : 1;
};
union leaf_0x2_regs {
struct leaf_0x2_reg reg[4];
u32 regv[4];
u8 desc[16];
};
/*
* Leaf 0x2 1-byte descriptors' cache types
* To be used for their mappings at cpuid_0x2_table[]
*
* Start at 1 since type 0 is reserved for HW byte descriptors which are
* not recognized by the kernel; i.e., those without an explicit mapping.
*/
enum _cache_table_type {
CACHE_L1_INST = 1,
CACHE_L1_DATA,
CACHE_L2,
CACHE_L3
/* Adjust __TLB_TABLE_TYPE_BEGIN before adding more types */
} __packed;
#ifndef __CHECKER__
static_assert(sizeof(enum _cache_table_type) == 1);
#endif
/*
* Ensure that leaf 0x2 cache and TLB type values do not intersect,
* since they share the same type field at struct cpuid_0x2_table.
*/
#define __TLB_TABLE_TYPE_BEGIN (CACHE_L3 + 1)
/*
* Leaf 0x2 1-byte descriptors' TLB types
* To be used for their mappings at cpuid_0x2_table[]
*/
enum _tlb_table_type {
TLB_INST_4K = __TLB_TABLE_TYPE_BEGIN,
TLB_INST_4M,
TLB_INST_2M_4M,
TLB_INST_ALL,
TLB_DATA_4K,
TLB_DATA_4M,
TLB_DATA_2M_4M,
TLB_DATA_4K_4M,
TLB_DATA_1G,
TLB_DATA_1G_2M_4M,
TLB_DATA0_4K,
TLB_DATA0_4M,
TLB_DATA0_2M_4M,
STLB_4K,
STLB_4K_2M,
} __packed;
Annotation
- Immediate include surface: `linux/build_bug.h`, `linux/types.h`, `asm/cpuid/leaf_types.h`.
- Detected declarations: `struct cpuid_regs`, `struct leaf_0x2_reg`, `struct leaf_0x2_table`, `struct leaf_parse_info`, `struct cpuid_leaves`, `struct cpuid_table`, `enum cpuid_regs_idx`, `enum _cache_table_type`, `enum _tlb_table_type`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.