arch/x86/include/asm/paravirt-spinlock.h
Source file repositories/reference/linux-study-clean/arch/x86/include/asm/paravirt-spinlock.h
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/include/asm/paravirt-spinlock.h- Extension
.h- Size
- 3922 bytes
- Lines
- 146
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/paravirt_types.hasm/spinlock_types.h
Detected Declarations
struct qspinlockstruct pv_lock_opsfunction pv_queued_spin_lock_slowpathfunction pv_queued_spin_unlockfunction pv_vcpu_is_preemptedfunction smp_store_releasefunction queued_spin_lock_slowpathfunction queued_spin_unlockfunction vcpu_is_preemptedfunction pv_waitfunction pv_kickfunction virt_spin_lock
Annotated Snippet
struct pv_lock_ops {
void (*queued_spin_lock_slowpath)(struct qspinlock *lock, u32 val);
struct paravirt_callee_save queued_spin_unlock;
void (*wait)(u8 *ptr, u8 val);
void (*kick)(int cpu);
struct paravirt_callee_save vcpu_is_preempted;
} __no_randomize_layout;
extern struct pv_lock_ops pv_ops_lock;
#ifdef CONFIG_PARAVIRT_SPINLOCKS
extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
extern void __pv_init_lock_hash(void);
extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
extern void __raw_callee_save___pv_queued_spin_unlock(struct qspinlock *lock);
extern bool nopvspin;
static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
u32 val)
{
PVOP_VCALL2(pv_ops_lock, queued_spin_lock_slowpath, lock, val);
}
static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
{
PVOP_ALT_VCALLEE1(pv_ops_lock, queued_spin_unlock, lock,
"movb $0, (%%" _ASM_ARG1 ")",
ALT_NOT(X86_FEATURE_PVUNLOCK));
}
static __always_inline bool pv_vcpu_is_preempted(long cpu)
{
return PVOP_ALT_CALLEE1(bool, pv_ops_lock, vcpu_is_preempted, cpu,
"xor %%eax, %%eax",
ALT_NOT(X86_FEATURE_VCPUPREEMPT));
}
#define queued_spin_unlock queued_spin_unlock
/**
* queued_spin_unlock - release a queued spinlock
* @lock : Pointer to queued spinlock structure
*
* A smp_store_release() on the least-significant byte.
*/
static inline void native_queued_spin_unlock(struct qspinlock *lock)
{
smp_store_release(&lock->locked, 0);
}
static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
{
pv_queued_spin_lock_slowpath(lock, val);
}
static inline void queued_spin_unlock(struct qspinlock *lock)
{
kcsan_release();
pv_queued_spin_unlock(lock);
}
#define vcpu_is_preempted vcpu_is_preempted
static inline bool vcpu_is_preempted(long cpu)
{
return pv_vcpu_is_preempted(cpu);
}
static __always_inline void pv_wait(u8 *ptr, u8 val)
{
PVOP_VCALL2(pv_ops_lock, wait, ptr, val);
}
static __always_inline void pv_kick(int cpu)
{
PVOP_VCALL1(pv_ops_lock, kick, cpu);
}
void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock);
bool __raw_callee_save___native_vcpu_is_preempted(long cpu);
#endif /* CONFIG_PARAVIRT_SPINLOCKS */
void __init native_pv_lock_init(void);
__visible void __native_queued_spin_unlock(struct qspinlock *lock);
bool pv_is_native_spin_unlock(void);
__visible bool __native_vcpu_is_preempted(long cpu);
bool pv_is_native_vcpu_is_preempted(void);
/*
* virt_spin_lock_key - disables by default the virt_spin_lock() hijack.
Annotation
- Immediate include surface: `asm/paravirt_types.h`, `asm/spinlock_types.h`.
- Detected declarations: `struct qspinlock`, `struct pv_lock_ops`, `function pv_queued_spin_lock_slowpath`, `function pv_queued_spin_unlock`, `function pv_vcpu_is_preempted`, `function smp_store_release`, `function queued_spin_lock_slowpath`, `function queued_spin_unlock`, `function vcpu_is_preempted`, `function pv_wait`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.