arch/x86/include/asm/processor.h
Source file repositories/reference/linux-study-clean/arch/x86/include/asm/processor.h
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/include/asm/processor.h- Extension
.h- Size
- 20244 bytes
- Lines
- 788
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/processor-flags.hasm/math_emu.hasm/segment.hasm/types.huapi/asm/sigcontext.hasm/current.hasm/cpufeatures.hasm/cpuid/types.hasm/page.hasm/pgtable_types.hasm/percpu.hasm/desc_defs.hasm/nops.hasm/special_insns.hasm/fpu/types.hasm/unwind_hints.hasm/vmxfeatures.hasm/vdso/processor.hasm/shstk.hlinux/personality.hlinux/cache.hlinux/threads.hlinux/math64.hlinux/err.hlinux/irqflags.hlinux/mem_encrypt.hasm/paravirt.h
Detected Declarations
struct task_structstruct mm_structstruct io_bitmapstruct vm86struct cpuinfo_topologystruct cpuinfo_x86struct x86_hw_tssstruct x86_hw_tssstruct entry_stackstruct entry_stack_pagestruct x86_io_bitmapstruct tss_structstruct irq_stackstruct perf_eventstruct thread_structenum idle_boot_overrideenum l1tf_mitigationsenum mds_mitigationsfunction l1tf_pfn_limitfunction read_cr3_pafunction native_read_cr3_pafunction load_cr3function cpu_kernelmode_gs_basefunction arch_thread_struct_whitelistfunction native_load_sp0function native_swapgsfunction current_top_of_stackfunction on_thread_stackfunction load_sp0function IIIfunction prefetchwfunction per_cpu_llc_idfunction per_cpu_l2c_idfunction per_cpu_core_idfunction amd_clear_dividerfunction amd_clear_dividerfunction weak_wrmsr_fence
Annotated Snippet
struct cpuinfo_topology {
// Real APIC ID read from the local APIC
u32 apicid;
// The initial APIC ID provided by CPUID
u32 initial_apicid;
// Physical package ID
u32 pkg_id;
// Physical die ID on AMD, Relative on Intel
u32 die_id;
// Compute unit ID - AMD specific
u32 cu_id;
// Core ID relative to the package
u32 core_id;
// Logical ID mappings
u32 logical_pkg_id;
u32 logical_die_id;
u32 logical_core_id;
// AMD Node ID and Nodes per Package info
u32 amd_node_id;
// Cache level topology IDs
u32 llc_id;
u32 l2c_id;
// Hardware defined CPU-type
union {
u32 cpu_type;
struct {
// CPUID.1A.EAX[23-0]
u32 intel_native_model_id :24;
// CPUID.1A.EAX[31-24]
u32 intel_type :8;
};
struct {
// CPUID 0x80000026.EBX
u32 amd_num_processors :16,
amd_power_eff_ranking :8,
amd_native_model_id :4,
amd_type :4;
};
};
};
struct cpuinfo_x86 {
union {
/*
* The particular ordering (low-to-high) of (vendor,
* family, model) is done in case range of models, like
* it is usually done on AMD, need to be compared.
*/
struct {
__u8 x86_model;
/* CPU family */
__u8 x86;
/* CPU vendor */
__u8 x86_vendor;
__u8 x86_reserved;
};
/* combined vendor, family, model */
__u32 x86_vfm;
};
__u8 x86_stepping;
union {
// MSR_IA32_PLATFORM_ID[52-50]
__u8 intel_platform_id;
__u8 amd_unused;
};
#ifdef CONFIG_X86_64
/* Number of 4K pages in DTLB/ITLB combined(in pages): */
int x86_tlbsize;
#endif
#ifdef CONFIG_X86_VMX_FEATURE_NAMES
__u32 vmx_capability[NVMXINTS];
#endif
__u8 x86_virt_bits;
__u8 x86_phys_bits;
/* Max extended CPUID function supported: */
__u32 extended_cpuid_level;
/* Maximum supported CPUID level, -1=no CPUID: */
int cpuid_level;
/*
* Align to size of unsigned long because the x86_capability array
* is passed to bitops which require the alignment. Use unnamed
* union to enforce the array is aligned to size of unsigned long.
Annotation
- Immediate include surface: `asm/processor-flags.h`, `asm/math_emu.h`, `asm/segment.h`, `asm/types.h`, `uapi/asm/sigcontext.h`, `asm/current.h`, `asm/cpufeatures.h`, `asm/cpuid/types.h`.
- Detected declarations: `struct task_struct`, `struct mm_struct`, `struct io_bitmap`, `struct vm86`, `struct cpuinfo_topology`, `struct cpuinfo_x86`, `struct x86_hw_tss`, `struct x86_hw_tss`, `struct entry_stack`, `struct entry_stack_page`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.