arch/x86/include/asm/seamldr.h

File Facts

System

Linux kernel

Corpus path

arch/x86/include/asm/seamldr.h

Extension

.h

Size

891 bytes

Lines

39

Domain

Architecture Layer

Bucket

arch/x86

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/types.h

Detected Declarations

• struct seamldr_info

Annotated Snippet

struct seamldr_info {
	u32	version;
	u32	attributes;
	u32	vendor_id;
	u32	build_date;
	u16	build_num;
	u16	minor_version;
	u16	major_version;
	u16	update_version;
	u32	acm_x2apicid;
	u32	num_remaining_updates;
	u8	seam_info[128];
	u8	seam_ready;
	u8	seam_debug;
	u8	p_seam_ready;
	u8	reserved[93];
} __packed __aligned(256);

static_assert(sizeof(struct seamldr_info) == 256);

int seamldr_get_info(struct seamldr_info *seamldr_info);
int seamldr_install_module(const u8 *data, u32 data_len);
void seamldr_lock_module_update(void);
void seamldr_unlock_module_update(void);

#endif /* _ASM_X86_SEAMLDR_H */

Annotation

• Immediate include surface: `linux/types.h`.
• Detected declarations: `struct seamldr_info`.
• Atlas domain: Architecture Layer / arch/x86.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.