arch/x86/include/asm/suspend_32.h

File Facts

System

Linux kernel

Corpus path

arch/x86/include/asm/suspend_32.h

Extension

.h

Size

897 bytes

Lines

39

Domain

Architecture Layer

Bucket

arch/x86

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• asm/desc.h
• asm/fpu/api.h
• asm/msr.h

Detected Declarations

• struct saved_context

Annotated Snippet

struct saved_context {
	unsigned long cr0, cr2, cr3, cr4;
	u64 misc_enable;
	struct saved_msrs saved_msrs;
	struct desc_ptr gdt_desc;
	struct desc_ptr idt;
	u16 ldt;
	u16 tss;
	unsigned long tr;
	unsigned long safety;
	unsigned long return_address;
	/*
	 * On x86_32, all segment registers except gs are saved at kernel
	 * entry in pt_regs.
	 */
	u16 gs;
	bool misc_enable_saved;
} __attribute__((packed));

/* routines for saving/restoring kernel state */
extern char core_restore_code[];
extern char restore_registers[];

#endif /* _ASM_X86_SUSPEND_32_H */

Annotation

• Immediate include surface: `asm/desc.h`, `asm/fpu/api.h`, `asm/msr.h`.
• Detected declarations: `struct saved_context`.
• Atlas domain: Architecture Layer / arch/x86.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.