arch/x86/kernel/acpi/boot.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/acpi/boot.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/acpi/boot.c- Extension
.c- Size
- 46038 bytes
- Lines
- 1871
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/acpi.hlinux/acpi_pmtmr.hlinux/efi.hlinux/cpumask.hlinux/export.hlinux/dmi.hlinux/irq.hlinux/slab.hlinux/memblock.hlinux/ioport.hlinux/pci.hlinux/efi-bgrt.hlinux/serial_core.hlinux/pgtable.hxen/xen.hasm/e820/api.hasm/irqdomain.hasm/pci_x86.hasm/io_apic.hasm/apic.hasm/io.hasm/mpspec.hasm/smp.hasm/i8259.hasm/setup.hasm/hypervisor.hsleep.hasm/proto.hacpi/processor.hasm/hpet.h
Detected Declarations
function early_memremapfunction __acpi_unmap_tablefunction acpi_parse_madtfunction acpi_is_processor_usablefunction acpi_parse_x2apicfunction acpi_check_lapicfunction acpi_parse_lapicfunction acpi_parse_sapicfunction acpi_parse_lapic_addr_ovrfunction acpi_parse_x2apic_nmifunction acpi_parse_lapic_nmifunction mp_override_legacy_irqfunction mp_config_acpi_gsifunction mp_register_ioapic_irqfunction acpi_parse_ioapicfunction acpi_sci_ioapic_setupfunction acpi_parse_int_src_ovrfunction acpi_parse_nmi_srcfunction acpi_pic_sci_set_triggerfunction acpi_gsi_to_irqfunction acpi_isa_irq_to_gsifunction acpi_register_gsi_picfunction acpi_register_gsi_ioapicfunction acpi_unregister_gsi_ioapicfunction acpi_register_gsifunction acpi_unregister_gsifunction acpi_set_irq_model_ioapicfunction acpi_map_cpu2nodefunction acpi_map_cpufunction acpi_unmap_cpufunction acpi_register_ioapicfunction acpi_unregister_ioapicfunction acpi_ioapic_registeredfunction acpi_parse_sbffunction acpi_parse_hpetfunction hpet_insert_resourcefunction acpi_parse_fadtfunction early_acpi_parse_madt_lapic_addr_ovrfunction acpi_parse_madt_lapic_entriesfunction mp_config_acpi_legacy_irqsfunction acpi_parse_madt_ioapic_entriesfunction acpi_parse_madt_ioapic_entriesfunction early_acpi_process_madtfunction acpi_process_madtfunction disable_acpi_irqfunction disable_acpi_pcifunction disable_acpi_xsdtfunction dmi_disable_acpi
Annotated Snippet
if (acpi_skip_timer_override) {
pr_warn("BIOS IRQ0 override ignored.\n");
return 0;
}
if ((intsrc->global_irq == 2) && acpi_fix_pin2_polarity
&& (intsrc->inti_flags & ACPI_MADT_POLARITY_MASK)) {
intsrc->inti_flags &= ~ACPI_MADT_POLARITY_MASK;
pr_warn("BIOS IRQ0 pin2 override: forcing polarity to high active.\n");
}
}
mp_override_legacy_irq(intsrc->source_irq,
intsrc->inti_flags & ACPI_MADT_POLARITY_MASK,
(intsrc->inti_flags & ACPI_MADT_TRIGGER_MASK) >> 2,
intsrc->global_irq);
return 0;
}
static int __init
acpi_parse_nmi_src(union acpi_subtable_headers * header, const unsigned long end)
{
struct acpi_madt_nmi_source *nmi_src = NULL;
nmi_src = (struct acpi_madt_nmi_source *)header;
if (BAD_MADT_ENTRY(nmi_src, end))
return -EINVAL;
acpi_table_print_madt_entry(&header->common);
/* TBD: Support nimsrc entries? */
return 0;
}
#endif /* CONFIG_X86_IO_APIC */
/*
* acpi_pic_sci_set_trigger()
*
* use ELCR to set PIC-mode trigger type for SCI
*
* If a PIC-mode SCI is not recognized or gives spurious IRQ7's
* it may require Edge Trigger -- use "acpi_sci=edge"
*
* Port 0x4d0-4d1 are ELCR1 and ELCR2, the Edge/Level Control Registers
* for the 8259 PIC. bit[n] = 1 means irq[n] is Level, otherwise Edge.
* ELCR1 is IRQs 0-7 (IRQ 0, 1, 2 must be 0)
* ELCR2 is IRQs 8-15 (IRQ 8, 13 must be 0)
*/
void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
{
unsigned int mask = 1 << irq;
unsigned int old, new;
/* Real old ELCR mask */
old = inb(PIC_ELCR1) | (inb(PIC_ELCR2) << 8);
/*
* If we use ACPI to set PCI IRQs, then we should clear ELCR
* since we will set it correctly as we enable the PCI irq
* routing.
*/
new = acpi_noirq ? old : 0;
/*
* Update SCI information in the ELCR, it isn't in the PCI
* routing tables..
*/
switch (trigger) {
case 1: /* Edge - clear */
new &= ~mask;
break;
case 3: /* Level - set */
new |= mask;
break;
}
if (old == new)
return;
pr_warn("setting ELCR to %04x (from %04x)\n", new, old);
outb(new, PIC_ELCR1);
outb(new >> 8, PIC_ELCR2);
}
int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
Annotation
- Immediate include surface: `linux/init.h`, `linux/acpi.h`, `linux/acpi_pmtmr.h`, `linux/efi.h`, `linux/cpumask.h`, `linux/export.h`, `linux/dmi.h`, `linux/irq.h`.
- Detected declarations: `function early_memremap`, `function __acpi_unmap_table`, `function acpi_parse_madt`, `function acpi_is_processor_usable`, `function acpi_parse_x2apic`, `function acpi_check_lapic`, `function acpi_parse_lapic`, `function acpi_parse_sapic`, `function acpi_parse_lapic_addr_ovr`, `function acpi_parse_x2apic_nmi`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.