arch/x86/kernel/aperture_64.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/aperture_64.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/aperture_64.c- Extension
.c- Size
- 15934 bytes
- Lines
- 562
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/kcore.hlinux/types.hlinux/init.hlinux/memblock.hlinux/mmzone.hlinux/pci_ids.hlinux/pci.hlinux/bitops.hlinux/suspend.hasm/e820/api.hasm/io.hasm/iommu.hasm/gart.hasm/pci-direct.hasm/dma.hasm/amd/nb.hasm/x86_init.hlinux/crash_dump.h
Detected Declarations
function gart_mem_pfn_is_ramfunction gart_oldmem_pfn_is_ramfunction exclude_from_corefunction exclude_from_corefunction find_capfunction read_agpfunction search_agp_bridgefunction parse_gart_memfunction early_gart_iommu_checkfunction gart_iommu_hole_init
Annotated Snippet
switch (class >> 16) {
case PCI_CLASS_BRIDGE_HOST:
case PCI_CLASS_BRIDGE_OTHER: /* needed? */
/* AGP bridge? */
cap = find_cap(bus, slot, func,
PCI_CAP_ID_AGP);
if (!cap)
break;
*valid_agp = 1;
return read_agp(bus, slot, func, cap,
order);
}
type = read_pci_config_byte(bus, slot, func,
PCI_HEADER_TYPE);
if (!(type & PCI_HEADER_TYPE_MFD))
break;
}
}
}
pr_info("No AGP bridge found\n");
return 0;
}
static bool gart_fix_e820 __initdata = true;
static int __init parse_gart_mem(char *p)
{
return kstrtobool(p, &gart_fix_e820);
}
early_param("gart_fix_e820", parse_gart_mem);
/*
* With kexec/kdump, if the first kernel doesn't shut down the GART and the
* second kernel allocates a different GART region, there might be two
* overlapping GART regions present:
*
* - the first still used by the GART initialized in the first kernel.
* - (sub-)set of it used as normal RAM by the second kernel.
*
* which leads to memory corruptions and a kernel panic eventually.
*
* This can also happen if the BIOS has forgotten to mark the GART region
* as reserved.
*
* Try to update the e820 map to mark that new region as reserved.
*/
void __init early_gart_iommu_check(void)
{
u32 agp_aper_order = 0;
int i, fix, slot, valid_agp = 0;
u32 ctl;
u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
u64 aper_base = 0, last_aper_base = 0;
int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
if (!amd_gart_present())
return;
if (!early_pci_allowed())
return;
/* This is mostly duplicate of iommu_hole_init */
search_agp_bridge(&agp_aper_order, &valid_agp);
fix = 0;
for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
int bus;
int dev_base, dev_limit;
bus = amd_nb_bus_dev_ranges[i].bus;
dev_base = amd_nb_bus_dev_ranges[i].dev_base;
dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
for (slot = dev_base; slot < dev_limit; slot++) {
if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
continue;
ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
aper_enabled = ctl & GARTEN;
aper_order = (ctl >> 1) & 7;
aper_size = (32 * 1024 * 1024) << aper_order;
aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
aper_base <<= 25;
if (last_valid) {
if ((aper_order != last_aper_order) ||
(aper_base != last_aper_base) ||
(aper_enabled != last_aper_enabled)) {
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/kcore.h`, `linux/types.h`, `linux/init.h`, `linux/memblock.h`, `linux/mmzone.h`, `linux/pci_ids.h`, `linux/pci.h`.
- Detected declarations: `function gart_mem_pfn_is_ram`, `function gart_oldmem_pfn_is_ram`, `function exclude_from_core`, `function exclude_from_core`, `function find_cap`, `function read_agp`, `function search_agp_bridge`, `function parse_gart_mem`, `function early_gart_iommu_check`, `function gart_iommu_hole_init`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.