arch/x86/kernel/cpu/cacheinfo.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/cpu/cacheinfo.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/cpu/cacheinfo.c- Extension
.c- Size
- 20375 bytes
- Lines
- 821
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cacheinfo.hlinux/cpu.hlinux/cpuhotplug.hlinux/stop_machine.hasm/amd/nb.hasm/cacheinfo.hasm/cpufeature.hasm/cpuid/api.hasm/mtrr.hasm/smp.hasm/tlbflush.hcpu.h
Detected Declarations
struct _cpuid4_infoenum _cache_typefunction legacy_amd_cpuid4function cpuid4_info_fill_donefunction amd_fill_cpuid4_infofunction intel_fill_cpuid4_infofunction fill_cpuid4_infofunction find_num_cache_leavesfunction CPUIDfunction cacheinfo_amd_init_llc_idfunction cacheinfo_hygon_init_llc_idfunction init_amd_cacheinfofunction init_hygon_cacheinfofunction intel_cacheinfo_donefunction CPUIDfunction calc_cache_topo_idfunction intel_cacheinfo_0x4function init_intel_cacheinfofunction __cache_amd_cpumap_setupfunction for_each_cpufunction for_each_cpufunction for_each_online_cpufunction for_each_online_cpufunction __cache_cpumap_setupfunction for_each_online_cpufunction ci_info_initfunction init_cache_levelfunction populate_cache_leavesfunction maybe_flush_cachesfunction cache_disablefunction cache_enablefunction cache_cpu_initfunction set_cache_aps_delayed_initfunction get_cache_aps_delayed_initfunction cache_rendezvous_handlerfunction cache_bp_initfunction cache_bp_restorefunction cache_ap_onlinefunction cache_ap_offlinefunction cache_aps_initfunction cache_ap_register
Annotated Snippet
struct _cpuid4_info {
union _cpuid4_leaf_eax eax;
union _cpuid4_leaf_ebx ebx;
union _cpuid4_leaf_ecx ecx;
unsigned int id;
unsigned long size;
};
/* Map CPUID(0x4) EAX.cache_type to <linux/cacheinfo.h> types */
static const enum cache_type cache_type_map[] = {
[CTYPE_NULL] = CACHE_TYPE_NOCACHE,
[CTYPE_DATA] = CACHE_TYPE_DATA,
[CTYPE_INST] = CACHE_TYPE_INST,
[CTYPE_UNIFIED] = CACHE_TYPE_UNIFIED,
};
/*
* Fallback AMD CPUID(0x4) emulation
* AMD CPUs with TOPOEXT can just use CPUID(0x8000001d)
*
* @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache should
* be determined from CPUID(0x8000001d) instead of CPUID(0x80000006).
*/
#define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff
#define AMD_L2_L3_INVALID_ASSOC 0x9
union l1_cache {
struct {
unsigned line_size :8;
unsigned lines_per_tag :8;
unsigned assoc :8;
unsigned size_in_kb :8;
};
unsigned int val;
};
union l2_cache {
struct {
unsigned line_size :8;
unsigned lines_per_tag :4;
unsigned assoc :4;
unsigned size_in_kb :16;
};
unsigned int val;
};
union l3_cache {
struct {
unsigned line_size :8;
unsigned lines_per_tag :4;
unsigned assoc :4;
unsigned res :2;
unsigned size_encoded :14;
};
unsigned int val;
};
/* L2/L3 associativity mapping */
static const unsigned short assocs[] = {
[1] = 1,
[2] = 2,
[3] = 3,
[4] = 4,
[5] = 6,
[6] = 8,
[8] = 16,
[0xa] = 32,
[0xb] = 48,
[0xc] = 64,
[0xd] = 96,
[0xe] = 128,
[0xf] = AMD_CPUID4_FULLY_ASSOCIATIVE
};
static const unsigned char levels[] = { 1, 1, 2, 3 };
static const unsigned char types[] = { 1, 2, 3, 3 };
static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx)
{
unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb;
union l1_cache l1i, l1d, *l1;
union l2_cache l2;
union l3_cache l3;
eax->full = 0;
ebx->full = 0;
ecx->full = 0;
Annotation
- Immediate include surface: `linux/cacheinfo.h`, `linux/cpu.h`, `linux/cpuhotplug.h`, `linux/stop_machine.h`, `asm/amd/nb.h`, `asm/cacheinfo.h`, `asm/cpufeature.h`, `asm/cpuid/api.h`.
- Detected declarations: `struct _cpuid4_info`, `enum _cache_type`, `function legacy_amd_cpuid4`, `function cpuid4_info_fill_done`, `function amd_fill_cpuid4_info`, `function intel_fill_cpuid4_info`, `function fill_cpuid4_info`, `function find_num_cache_leaves`, `function CPUID`, `function cacheinfo_amd_init_llc_id`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.