arch/x86/kernel/cpu/feat_ctl.c

File Facts

System

Linux kernel

Corpus path

arch/x86/kernel/cpu/feat_ctl.c

Extension

.c

Size

6663 bytes

Lines

216

Domain

Architecture Layer

Bucket

arch/x86

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/tboot.h
• asm/cpu.h
• asm/cpufeature.h
• asm/msr-index.h
• asm/msr.h
• asm/processor.h
• asm/vmx.h

Detected Declarations

• enum vmx_feature_leafs
• function init_vmx_capabilities
• function nosgx
• function init_ia32_feat_ctl

Annotated Snippet

if (!enable_sgx_kvm) {
			pr_err_once("SGX Launch Control is locked. Disable SGX.\n");
			clear_cpu_cap(c, X86_FEATURE_SGX);
		} else {
			pr_err_once("SGX Launch Control is locked. Support SGX virtualization only.\n");
			clear_cpu_cap(c, X86_FEATURE_SGX_LC);
		}
	}
}

Annotation

• Immediate include surface: `linux/tboot.h`, `asm/cpu.h`, `asm/cpufeature.h`, `asm/msr-index.h`, `asm/msr.h`, `asm/processor.h`, `asm/vmx.h`.
• Detected declarations: `enum vmx_feature_leafs`, `function init_vmx_capabilities`, `function nosgx`, `function init_ia32_feat_ctl`.
• Atlas domain: Architecture Layer / arch/x86.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.