arch/x86/kernel/cpu/mce/amd.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/cpu/mce/amd.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/cpu/mce/amd.c- Extension
.c- Size
- 32483 bytes
- Lines
- 1286
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/interrupt.hlinux/notifier.hlinux/kobject.hlinux/percpu.hlinux/errno.hlinux/sched.hlinux/sysfs.hlinux/slab.hlinux/init.hlinux/cpu.hlinux/smp.hlinux/string.hasm/traps.hasm/apic.hasm/mce.hasm/msr.hasm/trace/irq_vectors.hinternal.h
Detected Declarations
struct mce_amd_cpu_datastruct smca_hwidstruct smca_bankstruct threshold_blockstruct threshold_bankstruct thresh_restartstruct threshold_attrfunction smca_get_bank_typefunction default_deferred_error_interruptfunction smca_configurefunction lvt_interrupt_supportedfunction lvt_off_validfunction threshold_restart_blockfunction threshold_restart_bankfunction list_for_each_entry_safefunction get_thr_limitfunction mce_threshold_block_initfunction setup_APIC_mce_thresholdfunction get_block_addressfunction prepare_threshold_blockfunction amd_filter_mcefunction disable_err_thresholdingfunction amd_apply_cpu_quirksfunction smca_enable_interrupt_vectorsfunction mce_amd_feature_initfunction smca_bsp_initfunction Northbridgefunction smca_mce_is_memory_errorfunction amd_mce_is_memory_errorfunction northbridgefunction amd_deferred_error_interruptfunction mce_amd_handle_stormfunction amd_reset_thr_limitfunction amd_threshold_interruptfunction amd_clear_bankfunction store_interrupt_enablefunction store_threshold_limitfunction show_error_countfunction showfunction storefunction allocate_threshold_blocksfunction threshold_create_bankfunction threshold_block_releasefunction threshold_remove_bankfunction list_for_each_entry_safefunction __threshold_remove_devicefunction mce_threshold_remove_devicefunction mcheck_init_device
Annotated Snippet
struct mce_amd_cpu_data {
mce_banks_t thr_intr_banks;
mce_banks_t dfr_intr_banks;
u32 thr_intr_en: 1,
dfr_intr_en: 1,
__resv: 30;
};
static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data);
static const char * const th_names[] = {
"load_store",
"insn_fetch",
"combined_unit",
"decode_unit",
"northbridge",
"execution_unit",
};
static const char * const smca_umc_block_names[] = {
"dram_ecc",
"misc_umc"
};
#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
struct smca_hwid {
unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
u32 hwid_mcatype; /* (hwid,mcatype) tuple */
};
struct smca_bank {
const struct smca_hwid *hwid;
u32 id; /* Value of MCA_IPID[InstanceId]. */
u8 sysfs_id; /* Value used for sysfs name. */
u64 paddrv :1, /* Physical Address Valid bit in MCA_CONFIG */
__reserved :63;
};
static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
static const char * const smca_names[] = {
[SMCA_CS ... SMCA_CS_V2] = "coherent_station",
[SMCA_DACC_BE] = "dacc_be",
[SMCA_DACC_FE] = "dacc_fe",
[SMCA_DE] = "decode_unit",
[SMCA_EDDR5CMN] = "eddr5_cmn",
[SMCA_EX] = "execution_unit",
[SMCA_FP] = "floating_point",
[SMCA_GMI_PCS] = "gmi_pcs",
[SMCA_GMI_PHY] = "gmi_phy",
[SMCA_IF] = "insn_fetch",
[SMCA_L2_CACHE] = "l2_cache",
[SMCA_L3_CACHE] = "l3_cache",
[SMCA_LS ... SMCA_LS_V2] = "load_store",
[SMCA_MA_LLC] = "ma_llc",
[SMCA_MP5] = "mp5",
[SMCA_MPART] = "mpart",
[SMCA_MPASP ... SMCA_MPASP_V2] = "mpasp",
[SMCA_MPDACC] = "mpdacc",
[SMCA_MPDMA] = "mpdma",
[SMCA_MPM] = "mpm",
[SMCA_MPRAS] = "mpras",
[SMCA_NBIF] = "nbif",
[SMCA_NBIO] = "nbio",
[SMCA_PB] = "param_block",
[SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
[SMCA_PCIE_PL] = "pcie_pl",
[SMCA_PIE] = "pie",
[SMCA_PSP ... SMCA_PSP_V2] = "psp",
[SMCA_RESERVED] = "reserved",
[SMCA_SATA] = "sata",
[SMCA_SHUB] = "shub",
[SMCA_SMU ... SMCA_SMU_V2] = "smu",
[SMCA_SSBDCI] = "ssbdci",
/* UMC v2 is separate because both of them can exist in a single system. */
[SMCA_UMC] = "umc",
[SMCA_UMC_V2] = "umc_v2",
[SMCA_USB] = "usb",
[SMCA_USR_CP] = "usr_cp",
[SMCA_USR_DP] = "usr_dp",
[SMCA_WAFL_PHY] = "wafl_phy",
[SMCA_XGMI_PCS] = "xgmi_pcs",
[SMCA_XGMI_PHY] = "xgmi_phy",
};
static const char *smca_get_name(enum smca_bank_types t)
Annotation
- Immediate include surface: `linux/interrupt.h`, `linux/notifier.h`, `linux/kobject.h`, `linux/percpu.h`, `linux/errno.h`, `linux/sched.h`, `linux/sysfs.h`, `linux/slab.h`.
- Detected declarations: `struct mce_amd_cpu_data`, `struct smca_hwid`, `struct smca_bank`, `struct threshold_block`, `struct threshold_bank`, `struct thresh_restart`, `struct threshold_attr`, `function smca_get_bank_type`, `function default_deferred_error_interrupt`, `function smca_configure`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.