arch/x86/kernel/cpu/resctrl/monitor.c

Source file repositories/reference/linux-study-clean/arch/x86/kernel/cpu/resctrl/monitor.c

File Facts

System
Linux kernel
Corpus path
arch/x86/kernel/cpu/resctrl/monitor.c
Extension
.c
Size
16993 bytes
Lines
575
Domain
Architecture Layer
Bucket
arch/x86
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))) {
		r->mon.mbm_cntr_assignable = true;
		r->mon.mbm_cntr_configurable = true;
		cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx);
		r->mon.num_mbm_cntrs = (ebx & GENMASK(15, 0)) + 1;
		hw_res->mbm_cntr_assign_enabled = true;
	}

	r->mon_capable = true;

	return 0;
}

void __init intel_rdt_mbm_apply_quirk(void)
{
	int cf_index;

	cf_index = (boot_cpu_data.x86_cache_max_rmid + 1) / 8 - 1;
	if (cf_index >= ARRAY_SIZE(mbm_cf_table)) {
		pr_info("No MBM correction factor available\n");
		return;
	}

	mbm_cf_rmidthreshold = mbm_cf_table[cf_index].rmidthreshold;
	mbm_cf = mbm_cf_table[cf_index].cf;
}

static void resctrl_abmc_set_one_amd(void *arg)
{
	bool *enable = arg;

	if (*enable)
		msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
	else
		msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT);
}

/*
 * ABMC enable/disable requires update of L3_QOS_EXT_CFG MSR on all the CPUs
 * associated with all monitor domains.
 */
static void _resctrl_abmc_enable(struct rdt_resource *r, bool enable)
{
	struct rdt_l3_mon_domain *d;

	lockdep_assert_cpus_held();

	list_for_each_entry(d, &r->mon_domains, hdr.list) {
		on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_abmc_set_one_amd,
				 &enable, 1);
		resctrl_arch_reset_rmid_all(r, d);
	}
}

int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable)
{
	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);

	if (r->mon.mbm_cntr_assignable &&
	    hw_res->mbm_cntr_assign_enabled != enable) {
		_resctrl_abmc_enable(r, enable);
		hw_res->mbm_cntr_assign_enabled = enable;
	}

	return 0;
}

bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r)
{
	return resctrl_to_arch_res(r)->mbm_cntr_assign_enabled;
}

static void resctrl_abmc_config_one_amd(void *info)
{
	union l3_qos_abmc_cfg *abmc_cfg = info;

	wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full);
}

/*
 * Send an IPI to the domain to assign the counter to RMID, event pair.
 */
void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_l3_mon_domain *d,
			      enum resctrl_event_id evtid, u32 rmid, u32 closid,
			      u32 cntr_id, bool assign)
{
	struct rdt_hw_l3_mon_domain *hw_dom = resctrl_to_arch_mon_dom(d);
	union l3_qos_abmc_cfg abmc_cfg = { 0 };
	struct arch_mbm_state *am;

Annotation

Implementation Notes