arch/x86/kernel/devicetree.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/devicetree.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/devicetree.c- Extension
.c- Size
- 7902 bytes
- Lines
- 367
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/acpi.hlinux/export.hlinux/io.hlinux/interrupt.hlinux/list.hlinux/of.hlinux/of_fdt.hlinux/of_address.hlinux/of_platform.hlinux/of_irq.hlinux/libfdt.hlinux/slab.hlinux/pci.hlinux/of_pci.hlinux/initrd.hasm/acpi.hasm/irqdomain.hasm/hpet.hasm/apic.hasm/io_apic.hasm/pci_x86.hasm/setup.hasm/i8259.hasm/numa.hasm/prom.h
Detected Declarations
struct of_ioapic_typefunction add_dtbfunction add_bus_probefunction for_each_node_by_typefunction x86_of_pci_irq_enablefunction x86_of_pci_irq_disablefunction dtb_setup_hpetfunction dtb_wakeup_mailbox_setupfunction dtb_wakeup_mailbox_setupfunction dtb_cpu_setupfunction for_each_of_cpu_nodefunction dtb_lapic_setupfunction dt_irqdomain_allocfunction dtb_add_ioapicfunction dtb_ioapic_setupfunction dtb_ioapic_setupfunction x86_dtb_parse_smp_configfunction x86_flattree_get_configmodule init add_bus_probe
Annotated Snippet
device_initcall(add_bus_probe);
#ifdef CONFIG_PCI
struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
{
struct device_node *np;
for_each_node_by_type(np, "pci") {
const void *prop;
unsigned int bus_min;
prop = of_get_property(np, "bus-range", NULL);
if (!prop)
continue;
bus_min = be32_to_cpup(prop);
if (bus->number == bus_min)
return np;
}
return NULL;
}
static int x86_of_pci_irq_enable(struct pci_dev *dev)
{
u32 virq;
int ret;
u8 pin;
ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
if (ret)
return pcibios_err_to_errno(ret);
if (!pin)
return 0;
virq = of_irq_parse_and_map_pci(dev, 0, 0);
if (virq == 0)
return -EINVAL;
dev->irq = virq;
return 0;
}
static void x86_of_pci_irq_disable(struct pci_dev *dev)
{
}
void x86_of_pci_init(void)
{
pcibios_enable_irq = x86_of_pci_irq_enable;
pcibios_disable_irq = x86_of_pci_irq_disable;
}
#endif
static void __init dtb_setup_hpet(void)
{
#ifdef CONFIG_HPET_TIMER
struct device_node *dn;
struct resource r;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
if (!dn)
return;
ret = of_address_to_resource(dn, 0, &r);
if (ret) {
WARN_ON(1);
return;
}
hpet_address = r.start;
#endif
}
#if defined(CONFIG_X86_64) && defined(CONFIG_SMP)
#define WAKEUP_MAILBOX_SIZE 0x1000
#define WAKEUP_MAILBOX_ALIGN 0x1000
/** dtb_wakeup_mailbox_setup() - Parse the wakeup mailbox from the device tree
*
* Look for the presence of a wakeup mailbox in the DeviceTree. The mailbox is
* expected to follow the structure and operation described in the Multiprocessor
* Wakeup Structure of the ACPI specification.
*/
static void __init dtb_wakeup_mailbox_setup(void)
{
struct device_node *node;
struct resource res;
node = of_find_compatible_node(NULL, NULL, "intel,wakeup-mailbox");
if (!node)
return;
Annotation
- Immediate include surface: `linux/acpi.h`, `linux/export.h`, `linux/io.h`, `linux/interrupt.h`, `linux/list.h`, `linux/of.h`, `linux/of_fdt.h`, `linux/of_address.h`.
- Detected declarations: `struct of_ioapic_type`, `function add_dtb`, `function add_bus_probe`, `function for_each_node_by_type`, `function x86_of_pci_irq_enable`, `function x86_of_pci_irq_disable`, `function dtb_setup_hpet`, `function dtb_wakeup_mailbox_setup`, `function dtb_wakeup_mailbox_setup`, `function dtb_cpu_setup`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.