arch/x86/kernel/fpu/core.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/fpu/core.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/fpu/core.c- Extension
.c- Size
- 28628 bytes
- Lines
- 1011
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/fpu/api.hasm/fpu/regset.hasm/fpu/sched.hasm/fpu/signal.hasm/fpu/types.hasm/msr.hasm/traps.hasm/irq_regs.huapi/asm/kvm.hlinux/hardirq.hlinux/kvm_types.hlinux/pkeys.hlinux/vmalloc.hcontext.hinternal.hlegacy.hxstate.hasm/trace/fpu.h
Detected Declarations
function irq_fpu_usablefunction update_avx_timestampfunction fpregs_lockfunction restore_fpregs_from_fpstatefunction fpu_reset_from_exception_fixupfunction fpu_lock_guest_permissionsfunction fpu_alloc_guest_fpstatefunction fpu_free_guest_fpstatefunction fpu_enable_guest_xfd_featuresfunction fpu_update_guest_xfdfunction fpu_sync_guest_vmexit_xfd_statefunction fpu_swap_kvm_fpstatefunction fpu_copy_guest_fpstate_to_uabifunction fpu_copy_uabi_to_guest_fpstatefunction kernel_fpu_begin_maskfunction kernel_fpu_endfunction fpu_sync_fpstatefunction init_fpstate_copy_sizefunction fpstate_init_fxstatefunction fpstate_init_fstatefunction fpstate_init_userfunction __fpstate_resetfunction fpstate_resetfunction fpu_inherit_permsfunction update_fpu_shstkfunction fpu_clonefunction fpu_thread_struct_whitelistfunction fpu__dropfunction restore_fpregs_from_init_fpstatefunction fpu_reset_fpstate_regsfunction fpu__clear_user_statesfunction fpu_flush_threadfunction switch_fpu_returnfunction fpregs_lock_and_loadfunction trackingfunction fpregs_mark_activatefunction fpu__exception_codefunction fpu_idle_fpregsexport irq_fpu_usableexport kernel_fpu_begin_maskexport kernel_fpu_end
Annotated Snippet
if (boot_cpu_has(X86_FEATURE_FXSR)) {
cwd = fpu->fpstate->regs.fxsave.cwd;
swd = fpu->fpstate->regs.fxsave.swd;
} else {
cwd = (unsigned short)fpu->fpstate->regs.fsave.cwd;
swd = (unsigned short)fpu->fpstate->regs.fsave.swd;
}
err = swd & ~cwd;
} else {
/*
* The SIMD FPU exceptions are handled a little differently, as there
* is only a single status/control register. Thus, to determine which
* unmasked exception was caught we must mask the exception mask bits
* at 0x1f80, and then use these to mask the exception bits at 0x3f.
*/
unsigned short mxcsr = MXCSR_DEFAULT;
if (boot_cpu_has(X86_FEATURE_XMM))
mxcsr = fpu->fpstate->regs.fxsave.mxcsr;
err = ~(mxcsr >> 7) & mxcsr;
}
if (err & 0x001) { /* Invalid op */
/*
* swd & 0x240 == 0x040: Stack Underflow
* swd & 0x240 == 0x240: Stack Overflow
* User must clear the SF bit (0x40) if set
*/
return FPE_FLTINV;
} else if (err & 0x004) { /* Divide by Zero */
return FPE_FLTDIV;
} else if (err & 0x008) { /* Overflow */
return FPE_FLTOVF;
} else if (err & 0x012) { /* Denormal, Underflow */
return FPE_FLTUND;
} else if (err & 0x020) { /* Precision */
return FPE_FLTRES;
}
/*
* If we're using IRQ 13, or supposedly even some trap
* X86_TRAP_MF implementations, it's possible
* we get a spurious trap, which is not an error.
*/
return 0;
}
/*
* Initialize register state that may prevent from entering low-power idle.
* This function will be invoked from the cpuidle driver only when needed.
*/
noinstr void fpu_idle_fpregs(void)
{
/* Note: AMX_TILE being enabled implies XGETBV1 support */
if (cpu_feature_enabled(X86_FEATURE_AMX_TILE) &&
(xfeatures_in_use() & XFEATURE_MASK_XTILE)) {
tile_release();
__this_cpu_write(fpu_fpregs_owner_ctx, NULL);
}
}
Annotation
- Immediate include surface: `asm/fpu/api.h`, `asm/fpu/regset.h`, `asm/fpu/sched.h`, `asm/fpu/signal.h`, `asm/fpu/types.h`, `asm/msr.h`, `asm/traps.h`, `asm/irq_regs.h`.
- Detected declarations: `function irq_fpu_usable`, `function update_avx_timestamp`, `function fpregs_lock`, `function restore_fpregs_from_fpstate`, `function fpu_reset_from_exception_fixup`, `function fpu_lock_guest_permissions`, `function fpu_alloc_guest_fpstate`, `function fpu_free_guest_fpstate`, `function fpu_enable_guest_xfd_features`, `function fpu_update_guest_xfd`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.