arch/x86/kernel/irq.c

Source file repositories/reference/linux-study-clean/arch/x86/kernel/irq.c

File Facts

System
Linux kernel
Corpus path
arch/x86/kernel/irq.c
Extension
.c
Size
14773 bytes
Lines
533
Domain
Architecture Layer
Bucket
arch/x86
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct irq_stat_info {
	unsigned int	skip_vector;
	const char	*symbol;
	const char	*text;
};

#define DEFAULT_SUPPRESSED_VECTOR	UINT_MAX

#define ISS(idx, sym, txt) [IRQ_COUNT_##idx] = { .symbol = sym, .text = txt }

#define ITS(idx, sym, txt) [IRQ_COUNT_##idx] =				\
	{ .skip_vector = idx## _VECTOR, .symbol = sym, .text = txt }

#define IDS(idx, sym, txt) [IRQ_COUNT_##idx] =				\
	{ .skip_vector = DEFAULT_SUPPRESSED_VECTOR, .symbol = sym, .text = txt }

static const struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] = {
	ISS(NMI,			"NMI",	"  Non-maskable interrupts\n"),
#ifdef CONFIG_X86_LOCAL_APIC
	ISS(APIC_TIMER,			"LOC",	"  Local timer interrupts\n"),
	IDS(SPURIOUS,			"SPU",	"  Spurious interrupts\n"),
	ISS(APIC_PERF,			"PMI",	"  Performance monitoring interrupts\n"),
	ISS(IRQ_WORK,			"IWI",	"  IRQ work interrupts\n"),
	IDS(ICR_READ_RETRY,		"RTR",	"  APIC ICR read retries\n"),
	ISS(X86_PLATFORM_IPI,		"PLT",	"  Platform interrupts\n"),
#endif
#ifdef CONFIG_SMP
	ISS(RESCHEDULE,			"RES",	"  Rescheduling interrupts\n"),
	ISS(CALL_FUNCTION,		"CAL",	"  Function call interrupts\n"),
#endif
	ISS(TLB,			"TLB",	"  TLB shootdowns\n"),
#ifdef CONFIG_X86_THERMAL_VECTOR
	ISS(THERMAL_APIC,		"TRM",	"  Thermal event interrupts\n"),
#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
	ISS(THRESHOLD_APIC,		"THR",	"  Threshold APIC interrupts\n"),
#endif
#ifdef CONFIG_X86_MCE_AMD
	ISS(DEFERRED_ERROR,		"DFR",	"  Deferred Error APIC interrupts\n"),
#endif
#ifdef CONFIG_X86_MCE
	ISS(MCE_EXCEPTION,		"MCE",	"  Machine check exceptions\n"),
	ISS(MCE_POLL,			"MCP",	"  Machine check polls\n"),
#endif
#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
	ITS(HYPERVISOR_CALLBACK,	"HYP",	"  Hypervisor callback interrupts\n"),
#endif
#if IS_ENABLED(CONFIG_HYPERV)
	ITS(HYPERV_REENLIGHTENMENT,	"HRE",	"  Hyper-V reenlightenment interrupts\n"),
	ITS(HYPERV_STIMER0,		"HVS",	"  Hyper-V stimer0 interrupts\n"),
#endif
#if IS_ENABLED(CONFIG_KVM)
	ITS(POSTED_INTR,		"PIN",	"  Posted-interrupt notification event\n"),
	ITS(POSTED_INTR_NESTED,		"NPI",	"  Nested posted-interrupt event\n"),
	ITS(POSTED_INTR_WAKEUP,		"PIW",	"  Posted-interrupt wakeup event\n"),
#endif
#ifdef CONFIG_GUEST_PERF_EVENTS
	ISS(PERF_GUEST_MEDIATED_PMI,	"VPMI",	"  Perf Guest Mediated PMI\n"),
#endif
#ifdef CONFIG_X86_POSTED_MSI
	ISS(POSTED_MSI_NOTIFICATION,	"PMN",	"  Posted MSI notification event\n"),
#endif
	IDS(PIC_APIC_ERROR,		"ERR",	"  PIC/APIC error interrupts\n"),
#ifdef CONFIG_X86_IO_APIC
	IDS(IOAPIC_MISROUTED,		"MIS",	"  Misrouted IO/APIC interrupts\n"),
#endif
};

static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mostly;

static int __init irq_init_stats(void)
{
	const struct irq_stat_info *info = irq_stat_info;

	for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) {
		if (!info->skip_vector || (info->skip_vector != DEFAULT_SUPPRESSED_VECTOR &&
					   test_bit(info->skip_vector, system_vectors)))
			set_bit(i, irq_stat_count_show);
	}

#ifdef CONFIG_X86_LOCAL_APIC
	if (!x86_platform_ipi_callback)
		clear_bit(IRQ_COUNT_X86_PLATFORM_IPI, irq_stat_count_show);
#endif

#ifdef CONFIG_X86_POSTED_MSI
	if (!posted_msi_enabled())
		clear_bit(IRQ_COUNT_POSTED_MSI_NOTIFICATION, irq_stat_count_show);
#endif

Annotation

Implementation Notes