arch/x86/kernel/process_64.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/process_64.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/process_64.c- Extension
.c- Size
- 26446 bytes
- Lines
- 983
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cpu.hlinux/errno.hlinux/sched.hlinux/sched/task.hlinux/sched/task_stack.hlinux/fs.hlinux/kernel.hlinux/mm.hlinux/elfcore.hlinux/smp.hlinux/slab.hlinux/user.hlinux/interrupt.hlinux/delay.hlinux/export.hlinux/kvm_types.hlinux/ptrace.hlinux/notifier.hlinux/kprobes.hlinux/kdebug.hlinux/prctl.hlinux/uaccess.hlinux/io.hlinux/ftrace.hlinux/syscalls.hlinux/iommu.hasm/processor.hasm/pkru.hasm/fpu/sched.hasm/mmu_context.hasm/prctl.hasm/desc.h
Detected Declarations
enum which_selectorfunction Copyrightfunction release_threadfunction __rdgsbase_inactivefunction __wrgsbase_inactivefunction save_base_legacyfunction save_fsgsfunction registersfunction loadsegfunction load_seg_legacyfunction x86_pkru_loadfunction x86_fsgsbase_loadfunction x86_fsgsbase_read_taskfunction x86_gsbase_read_cpu_inactivefunction x86_gsbase_write_cpu_inactivefunction x86_fsbase_read_taskfunction x86_gsbase_read_taskfunction x86_fsbase_write_taskfunction x86_gsbase_write_taskfunction start_thread_commonfunction callfunction start_threadfunction compat_start_threadfunction switch_tofunction set_personality_64bitfunction __set_personality_x32function __set_personality_ia32function set_personality_ia32function prctl_map_vdsofunction enable_lam_funcfunction mm_enable_lamfunction prctl_enable_tagged_addrfunction do_arch_prctl_64export start_threadexport set_personality_ia32
Annotated Snippet
if (next_base == 0) {
/*
* Nasty case: on AMD CPUs, we need to forcibly zero
* the base.
*/
if (static_cpu_has_bug(X86_BUG_NULL_SEG)) {
loadseg(which, __USER_DS);
loadseg(which, next_index);
} else {
/*
* We could try to exhaustively detect cases
* under which we can skip the segment load,
* but there's really only one case that matters
* for performance: if both the previous and
* next states are fully zeroed, we can skip
* the load.
*
* (This assumes that prev_base == 0 has no
* false positives. This is the case on
* Intel-style CPUs.)
*/
if (likely(prev_index | next_index | prev_base))
loadseg(which, next_index);
}
} else {
if (prev_index != next_index)
loadseg(which, next_index);
wrmsrq(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE,
next_base);
}
} else {
/*
* The next task is using a real segment. Loading the selector
* is sufficient.
*/
loadseg(which, next_index);
}
}
/*
* Store prev's PKRU value and load next's PKRU value if they differ. PKRU
* is not XSTATE managed on context switch because that would require a
* lookup in the task's FPU xsave buffer and require to keep that updated
* in various places.
*/
static __always_inline void x86_pkru_load(struct thread_struct *prev,
struct thread_struct *next)
{
if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
return;
/* Stash the prev task's value: */
prev->pkru = rdpkru();
/*
* PKRU writes are slightly expensive. Avoid them when not
* strictly necessary:
*/
if (prev->pkru != next->pkru)
wrpkru(next->pkru);
}
static __always_inline void x86_fsgsbase_load(struct thread_struct *prev,
struct thread_struct *next)
{
if (static_cpu_has(X86_FEATURE_FSGSBASE)) {
/* Update the FS and GS selectors if they could have changed. */
if (unlikely(prev->fsindex || next->fsindex))
loadseg(FS, next->fsindex);
if (unlikely(prev->gsindex || next->gsindex))
loadseg(GS, next->gsindex);
/* Update the bases. */
wrfsbase(next->fsbase);
__wrgsbase_inactive(next->gsbase);
} else {
load_seg_legacy(prev->fsindex, prev->fsbase,
next->fsindex, next->fsbase, FS);
load_seg_legacy(prev->gsindex, prev->gsbase,
next->gsindex, next->gsbase, GS);
}
}
unsigned long x86_fsgsbase_read_task(struct task_struct *task,
unsigned short selector)
{
unsigned short idx = selector >> 3;
unsigned long base;
if (likely((selector & SEGMENT_TI_MASK) == 0)) {
Annotation
- Immediate include surface: `linux/cpu.h`, `linux/errno.h`, `linux/sched.h`, `linux/sched/task.h`, `linux/sched/task_stack.h`, `linux/fs.h`, `linux/kernel.h`, `linux/mm.h`.
- Detected declarations: `enum which_selector`, `function Copyright`, `function release_thread`, `function __rdgsbase_inactive`, `function __wrgsbase_inactive`, `function save_base_legacy`, `function save_fsgs`, `function registers`, `function loadseg`, `function load_seg_legacy`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: integration implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.