arch/x86/kernel/tsc_sync.c
Source file repositories/reference/linux-study-clean/arch/x86/kernel/tsc_sync.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kernel/tsc_sync.c- Extension
.c- Size
- 14552 bytes
- Lines
- 528
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/workqueue.hlinux/topology.hlinux/spinlock.hlinux/kernel.hlinux/smp.hlinux/nmi.hasm/msr.hasm/tsc.h
Detected Declarations
struct tsc_adjustfunction mark_tsc_async_resetsfunction tsc_verify_tsc_adjustfunction timerfunction start_sync_check_timerfunction tsc_sanitize_first_cpufunction tsc_store_and_check_tsc_adjustfunction tsc_store_and_check_tsc_adjustfunction check_tsc_warpfunction thenfunction alreadyfunction tsc_sync_mark_tsc_unstablefunction check_tsc_sync_sourcefunction check_tsc_sync_target
Annotated Snippet
struct tsc_adjust {
s64 bootval;
s64 adjusted;
unsigned long nextcheck;
bool warned;
};
static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
static struct timer_list tsc_sync_check_timer;
/*
* TSC's on different sockets may be reset asynchronously.
* This may cause the TSC ADJUST value on socket 0 to be NOT 0.
*/
bool __read_mostly tsc_async_resets;
void mark_tsc_async_resets(char *reason)
{
if (tsc_async_resets)
return;
tsc_async_resets = true;
pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
}
void tsc_verify_tsc_adjust(bool resume)
{
struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
s64 curval;
if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
return;
/* Skip unnecessary error messages if TSC already unstable */
if (check_tsc_unstable())
return;
/* Rate limit the MSR check */
if (!resume && time_before(jiffies, adj->nextcheck))
return;
adj->nextcheck = jiffies + HZ;
rdmsrq(MSR_IA32_TSC_ADJUST, curval);
if (adj->adjusted == curval)
return;
/* Restore the original value */
wrmsrq(MSR_IA32_TSC_ADJUST, adj->adjusted);
if (!adj->warned || resume) {
pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
smp_processor_id(), adj->adjusted, curval);
adj->warned = true;
}
}
/*
* Normally the tsc_sync will be checked every time system enters idle
* state, but there is still caveat that a system won't enter idle,
* either because it's too busy or configured purposely to not enter
* idle.
*
* So setup a periodic timer (every 10 minutes) to make sure the check
* is always on.
*/
#define SYNC_CHECK_INTERVAL (HZ * 600)
static void tsc_sync_check_timer_fn(struct timer_list *unused)
{
int next_cpu;
tsc_verify_tsc_adjust(false);
/* Run the check for all onlined CPUs in turn */
next_cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask);
if (next_cpu >= nr_cpu_ids)
next_cpu = cpumask_first(cpu_online_mask);
tsc_sync_check_timer.expires += SYNC_CHECK_INTERVAL;
add_timer_on(&tsc_sync_check_timer, next_cpu);
}
static int __init start_sync_check_timer(void)
{
if (!cpu_feature_enabled(X86_FEATURE_TSC_ADJUST) || tsc_clocksource_reliable)
return 0;
timer_setup(&tsc_sync_check_timer, tsc_sync_check_timer_fn, 0);
tsc_sync_check_timer.expires = jiffies + SYNC_CHECK_INTERVAL;
Annotation
- Immediate include surface: `linux/workqueue.h`, `linux/topology.h`, `linux/spinlock.h`, `linux/kernel.h`, `linux/smp.h`, `linux/nmi.h`, `asm/msr.h`, `asm/tsc.h`.
- Detected declarations: `struct tsc_adjust`, `function mark_tsc_async_resets`, `function tsc_verify_tsc_adjust`, `function timer`, `function start_sync_check_timer`, `function tsc_sanitize_first_cpu`, `function tsc_store_and_check_tsc_adjust`, `function tsc_store_and_check_tsc_adjust`, `function check_tsc_warp`, `function then`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.