arch/x86/kvm/svm/svm_onhyperv.c
Source file repositories/reference/linux-study-clean/arch/x86/kvm/svm/svm_onhyperv.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/kvm/svm/svm_onhyperv.c- Extension
.c- Size
- 1644 bytes
- Lines
- 64
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kvm_host.hasm/mshyperv.hsvm.hsvm_ops.hhyperv.hkvm_onhyperv.hsvm_onhyperv.h
Detected Declarations
function svm_hv_enable_l2_tlb_flushfunction svm_hv_hardware_setupfunction for_each_online_cpu
Annotated Snippet
for_each_online_cpu(cpu) {
struct hv_vp_assist_page *vp_ap =
hv_get_vp_assist_page(cpu);
if (!vp_ap)
continue;
vp_ap->nested_control.features.directhypercall = 1;
}
svm_x86_ops.enable_l2_tlb_flush =
svm_hv_enable_l2_tlb_flush;
}
}
Annotation
- Immediate include surface: `linux/kvm_host.h`, `asm/mshyperv.h`, `svm.h`, `svm_ops.h`, `hyperv.h`, `kvm_onhyperv.h`, `svm_onhyperv.h`.
- Detected declarations: `function svm_hv_enable_l2_tlb_flush`, `function svm_hv_hardware_setup`, `function for_each_online_cpu`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.