arch/x86/kvm/vmx/pmu_intel.h

File Facts

System

Linux kernel

Corpus path

arch/x86/kvm/vmx/pmu_intel.h

Extension

.h

Size

1082 bytes

Lines

44

Domain

Architecture Layer

Bucket

arch/x86

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/kvm_host.h
• cpuid.h

Detected Declarations

• struct lbr_desc
• function vcpu_get_perf_capabilities
• function fw_writes_is_enabled

Annotated Snippet

struct lbr_desc {
	/* Basic info about guest LBR records. */
	struct x86_pmu_lbr records;

	/*
	 * Emulate LBR feature via passthrough LBR registers when the
	 * per-vcpu guest LBR event is scheduled on the current pcpu.
	 *
	 * The records may be inaccurate if the host reclaims the LBR.
	 */
	struct perf_event *event;

	/* True if LBRs are marked as not intercepted in the MSR bitmap */
	bool msr_passthrough;
};

extern struct x86_pmu_lbr vmx_lbr_caps;

#endif /* __KVM_X86_VMX_PMU_INTEL_H */

Annotation

• Immediate include surface: `linux/kvm_host.h`, `cpuid.h`.
• Detected declarations: `struct lbr_desc`, `function vcpu_get_perf_capabilities`, `function fw_writes_is_enabled`.
• Atlas domain: Architecture Layer / arch/x86.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.