arch/x86/mm/tlb.c
Source file repositories/reference/linux-study-clean/arch/x86/mm/tlb.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/mm/tlb.c- Extension
.c- Size
- 53682 bytes
- Lines
- 1811
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/mm.hlinux/spinlock.hlinux/smp.hlinux/interrupt.hlinux/export.hlinux/cpu.hlinux/debugfs.hlinux/sched/smt.hlinux/task_work.hlinux/mmu_notifier.hlinux/mmu_context.hlinux/kvm_types.hasm/tlbflush.hasm/mmu_context.hasm/nospec-branch.hasm/cache.hasm/cacheflush.hasm/apic.hasm/msr.hasm/perf_event.hasm/tlb.hmm_internal.h
Detected Declarations
struct new_asidfunction kern_pcidfunction user_pcidfunction build_cr3function build_cr3_noflushfunction clear_asid_otherfunction choose_new_asidfunction reset_global_asid_spacefunction allocate_global_asidfunction mm_active_cpus_exceedsfunction use_global_asidfunction mm_free_global_asidfunction mm_needs_global_asidfunction ASIDsfunction finish_asid_transitionfunction for_each_cpufunction afunction broadcast_tlb_flushfunction inc_mm_tlb_genfunction invalidate_user_asidfunction load_new_mm_cr3function leave_mmfunction switch_mmfunction l1d_flush_force_sigbusfunction l1d_flush_evaluatefunction mm_mangle_tif_spec_bitsfunction cond_mitigationfunction cr4_update_pce_mmfunction cr4_update_pcefunction cr4_update_pce_mmfunction leave_mmfunction membarrierfunction protectionsfunction unuse_temporary_mmfunction initialize_tlbstate_and_flushfunction flush_tlb_funcfunction flushfunction should_flush_tlbfunction should_trim_cpumaskfunction native_flush_tlb_multifunction flush_tlb_multifunction put_flush_tlb_infofunction flush_tlb_mm_rangefunction flush_tlb_multifunction do_flush_tlb_allfunction flush_tlb_allfunction invlpgb_kernel_range_flushfunction do_kernel_range_flush
Annotated Snippet
static const struct file_operations fops_tlbflush = {
.read = tlbflush_read_file,
.write = tlbflush_write_file,
.llseek = default_llseek,
};
static int __init create_tlb_single_page_flush_ceiling(void)
{
debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
arch_debugfs_dir, NULL, &fops_tlbflush);
return 0;
}
late_initcall(create_tlb_single_page_flush_ceiling);
Annotation
- Immediate include surface: `linux/init.h`, `linux/mm.h`, `linux/spinlock.h`, `linux/smp.h`, `linux/interrupt.h`, `linux/export.h`, `linux/cpu.h`, `linux/debugfs.h`.
- Detected declarations: `struct new_asid`, `function kern_pcid`, `function user_pcid`, `function build_cr3`, `function build_cr3_noflush`, `function clear_asid_other`, `function choose_new_asid`, `function reset_global_asid_space`, `function allocate_global_asid`, `function mm_active_cpus_exceeds`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.