arch/x86/pci/irq.c
Source file repositories/reference/linux-study-clean/arch/x86/pci/irq.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/pci/irq.c- Extension
.c- Size
- 49086 bytes
- Lines
- 1811
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/kernel.hlinux/pci.hlinux/init.hlinux/interrupt.hlinux/dmi.hlinux/io.hlinux/smp.hlinux/spinlock.hasm/io_apic.hlinux/irq.hlinux/acpi.hasm/i8259.hasm/pc-conf-reg.hasm/pci_x86.h
Detected Declarations
struct irq_routerstruct irq_router_handlerfunction pirq_find_routing_tablefunction pirq_peer_trickfunction elcr_set_level_irqfunction Controllerfunction write_pc_conf_nybblefunction pirq_finali_getfunction pirq_finali_setfunction pirq_finali_lvlfunction read_config_nybblefunction write_config_nybblefunction pirq_ali_getfunction pirq_ali_setfunction pirq_esc_getfunction pirq_esc_setfunction pirq_piix_getfunction pirq_piix_setfunction Bridgefunction pirq_ib_setfunction pirq_via_getfunction pirq_via_setfunction pirq_via586_getfunction pirq_via586_setfunction pirq_ite_getfunction pirq_ite_setfunction pirq_opti_getfunction pirq_opti_setfunction pirq_cyrix_getfunction pirq_cyrix_setfunction pirq_sis497_getfunction pirq_sis497_setfunction differentlyfunction pirq_sis503_setfunction pirq_vlsi_getfunction pirq_vlsi_setfunction isfunction pirq_serverworks_setfunction pirq_amd756_getfunction pirq_amd756_setfunction pirq_pico_getfunction pirq_pico_setfunction pirq_bios_setfunction intel_router_probefunction via_router_probefunction vlsi_router_probefunction serverworks_router_probefunction sis_router_probe
Annotated Snippet
struct irq_router {
char *name;
u16 vendor, device;
int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
int new);
int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq,
int irq);
};
struct irq_router_handler {
u16 vendor;
int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
};
int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
/*
* Check passed address for the PCI IRQ Routing Table signature
* and perform checksum verification.
*/
static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr,
u8 *limit)
{
struct irq_routing_table *rt;
int i;
u8 sum;
rt = (struct irq_routing_table *)addr;
if (rt->signature != PIRQ_SIGNATURE ||
rt->version != PIRQ_VERSION ||
rt->size % 16 ||
rt->size < sizeof(struct irq_routing_table) ||
(limit && rt->size > limit - addr))
return NULL;
sum = 0;
for (i = 0; i < rt->size; i++)
sum += addr[i];
if (!sum) {
DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%lx\n",
__pa(rt));
return rt;
}
return NULL;
}
/*
* Handle the $IRT PCI IRQ Routing Table format used by AMI for its BCP
* (BIOS Configuration Program) external tool meant for tweaking BIOS
* structures without the need to rebuild it from sources. The $IRT
* format has been invented by AMI before Microsoft has come up with its
* $PIR format and a $IRT table is therefore there in some systems that
* lack a $PIR table.
*
* It uses the same PCI BIOS 2.1 format for interrupt routing entries
* themselves but has a different simpler header prepended instead,
* occupying 8 bytes, where a `$IRT' signature is followed by one byte
* specifying the total number of interrupt routing entries allocated in
* the table, then one byte specifying the actual number of entries used
* (which the BCP tool can take advantage of when modifying the table),
* and finally a 16-bit word giving the IRQs devoted exclusively to PCI.
* Unlike with the $PIR table there is no alignment guarantee.
*
* Given the similarity of the two formats the $IRT one is trivial to
* convert to the $PIR one, which we do here, except that obviously we
* have no information as to the router device to use, but we can handle
* it by matching PCI device IDs actually seen on the bus against ones
* that our individual routers recognise.
*
* Reportedly there is another $IRT table format where a 16-bit word
* follows the header instead that points to interrupt routing entries
* in a $PIR table provided elsewhere. In that case this code will not
* be reached though as the $PIR table will have been chosen instead.
*/
static inline struct irq_routing_table *pirq_convert_irt_table(u8 *addr,
u8 *limit)
{
struct irt_routing_table *ir;
struct irq_routing_table *rt;
u16 size;
u8 sum;
int i;
ir = (struct irt_routing_table *)addr;
if (ir->signature != IRT_SIGNATURE || !ir->used || ir->size < ir->used)
return NULL;
size = struct_size(ir, slots, ir->used);
Annotation
- Immediate include surface: `linux/types.h`, `linux/kernel.h`, `linux/pci.h`, `linux/init.h`, `linux/interrupt.h`, `linux/dmi.h`, `linux/io.h`, `linux/smp.h`.
- Detected declarations: `struct irq_router`, `struct irq_router_handler`, `function pirq_find_routing_table`, `function pirq_peer_trick`, `function elcr_set_level_irq`, `function Controller`, `function write_pc_conf_nybble`, `function pirq_finali_get`, `function pirq_finali_set`, `function pirq_finali_lvl`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.