arch/x86/pci/numachip.c
Source file repositories/reference/linux-study-clean/arch/x86/pci/numachip.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/pci/numachip.c- Extension
.c- Size
- 2881 bytes
- Lines
- 128
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.hasm/pci_x86.hasm/numachip/numachip.h
Detected Declarations
function pci_mmcfg_read_numachipfunction pci_mmcfg_write_numachipfunction pci_numachip_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Numascale NumaConnect-specific PCI code
*
* Copyright (C) 2012 Numascale AS. All rights reserved.
*
* Send feedback to <support@numascale.com>
*
* PCI accessor functions derived from mmconfig_64.c
*
*/
#include <linux/pci.h>
#include <asm/pci_x86.h>
#include <asm/numachip/numachip.h>
static u8 limit __read_mostly;
static inline char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
{
struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
if (cfg && cfg->virt)
return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
return NULL;
}
static int pci_mmcfg_read_numachip(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
char __iomem *addr;
/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
err: *value = -1;
return -EINVAL;
}
/* Ensure AMD Northbridges don't decode reads to other devices */
if (unlikely(bus == 0 && devfn >= limit)) {
*value = -1;
return 0;
}
rcu_read_lock();
addr = pci_dev_base(seg, bus, devfn);
if (!addr) {
rcu_read_unlock();
goto err;
}
switch (len) {
case 1:
*value = mmio_config_readb(addr + reg);
break;
case 2:
*value = mmio_config_readw(addr + reg);
break;
case 4:
*value = mmio_config_readl(addr + reg);
break;
}
rcu_read_unlock();
return 0;
}
static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 value)
{
char __iomem *addr;
/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
return -EINVAL;
/* Ensure AMD Northbridges don't decode writes to other devices */
if (unlikely(bus == 0 && devfn >= limit))
return 0;
rcu_read_lock();
addr = pci_dev_base(seg, bus, devfn);
if (!addr) {
rcu_read_unlock();
return -EINVAL;
}
switch (len) {
case 1:
mmio_config_writeb(addr + reg, value);
Annotation
- Immediate include surface: `linux/pci.h`, `asm/pci_x86.h`, `asm/numachip/numachip.h`.
- Detected declarations: `function pci_mmcfg_read_numachip`, `function pci_mmcfg_write_numachip`, `function pci_numachip_init`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.