arch/x86/platform/uv/uv_irq.c
Source file repositories/reference/linux-study-clean/arch/x86/platform/uv/uv_irq.c
File Facts
- System
- Linux kernel
- Corpus path
arch/x86/platform/uv/uv_irq.c- Extension
.c- Size
- 5557 bytes
- Lines
- 214
- Domain
- Architecture Layer
- Bucket
- arch/x86
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/export.hlinux/rbtree.hlinux/slab.hlinux/irq.hasm/irqdomain.hasm/apic.hasm/uv/uv_irq.hasm/uv/uv_hub.h
Detected Declarations
struct uv_irq_2_mmr_pnodefunction uv_program_mmrfunction uv_noopfunction uv_domain_allocfunction uv_domain_freefunction uv_domain_activatefunction uv_domain_deactivatefunction uv_setup_irqfunction uv_setup_irqexport uv_setup_irqexport uv_teardown_irq
Annotated Snippet
struct uv_irq_2_mmr_pnode {
unsigned long offset;
int pnode;
};
static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info)
{
unsigned long mmr_value;
struct uv_IO_APIC_route_entry *entry;
BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
sizeof(unsigned long));
mmr_value = 0;
entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
entry->vector = cfg->vector;
entry->delivery_mode = APIC_DELIVERY_MODE_FIXED;
entry->dest_mode = apic->dest_mode_logical;
entry->polarity = 0;
entry->trigger = 0;
entry->mask = 0;
entry->dest = cfg->dest_apicid;
uv_write_global_mmr64(info->pnode, info->offset, mmr_value);
}
static void uv_noop(struct irq_data *data) { }
static int
uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
bool force)
{
struct irq_data *parent = data->parent_data;
struct irq_cfg *cfg = irqd_cfg(data);
int ret;
ret = parent->chip->irq_set_affinity(parent, mask, force);
if (ret >= 0) {
uv_program_mmr(cfg, data->chip_data);
vector_schedule_cleanup(cfg);
}
return ret;
}
static struct irq_chip uv_irq_chip = {
.name = "UV-CORE",
.irq_mask = uv_noop,
.irq_unmask = uv_noop,
.irq_eoi = apic_ack_irq,
.irq_set_affinity = uv_set_irq_affinity,
};
static int uv_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
struct uv_irq_2_mmr_pnode *chip_data;
struct irq_alloc_info *info = arg;
struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
int ret;
if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_UV)
return -EINVAL;
chip_data = kmalloc_node(sizeof(*chip_data), GFP_KERNEL,
irq_data_get_node(irq_data));
if (!chip_data)
return -ENOMEM;
ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
if (ret >= 0) {
if (info->uv.limit == UV_AFFINITY_CPU)
irq_set_status_flags(virq, IRQ_NO_BALANCING);
chip_data->pnode = uv_blade_to_pnode(info->uv.blade);
chip_data->offset = info->uv.offset;
irq_domain_set_info(domain, virq, virq, &uv_irq_chip, chip_data,
handle_percpu_irq, NULL, info->uv.name);
} else {
kfree(chip_data);
}
return ret;
}
static void uv_domain_free(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs)
{
struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
Annotation
- Immediate include surface: `linux/export.h`, `linux/rbtree.h`, `linux/slab.h`, `linux/irq.h`, `asm/irqdomain.h`, `asm/apic.h`, `asm/uv/uv_irq.h`, `asm/uv/uv_hub.h`.
- Detected declarations: `struct uv_irq_2_mmr_pnode`, `function uv_program_mmr`, `function uv_noop`, `function uv_domain_alloc`, `function uv_domain_free`, `function uv_domain_activate`, `function uv_domain_deactivate`, `function uv_setup_irq`, `function uv_setup_irq`, `export uv_setup_irq`.
- Atlas domain: Architecture Layer / arch/x86.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.