arch/xtensa/include/asm/current.h
Source file repositories/reference/linux-study-clean/arch/xtensa/include/asm/current.h
File Facts
- System
- Linux kernel
- Corpus path
arch/xtensa/include/asm/current.h- Extension
.h- Size
- 750 bytes
- Lines
- 41
- Domain
- Architecture Layer
- Bucket
- arch/xtensa
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/thread_info.hlinux/thread_info.h
Detected Declarations
struct task_struct
Annotated Snippet
#ifndef _XTENSA_CURRENT_H
#define _XTENSA_CURRENT_H
#include <asm/thread_info.h>
#ifndef __ASSEMBLER__
#include <linux/thread_info.h>
struct task_struct;
static __always_inline struct task_struct *get_current(void)
{
return current_thread_info()->task;
}
#define current get_current()
register unsigned long current_stack_pointer __asm__("a1");
#else
#define GET_CURRENT(reg,sp) \
GET_THREAD_INFO(reg,sp); \
l32i reg, reg, TI_TASK \
#endif
#endif /* XTENSA_CURRENT_H */
Annotation
- Immediate include surface: `asm/thread_info.h`, `linux/thread_info.h`.
- Detected declarations: `struct task_struct`.
- Atlas domain: Architecture Layer / arch/xtensa.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.