arch/xtensa/include/asm/tlbflush.h
Source file repositories/reference/linux-study-clean/arch/xtensa/include/asm/tlbflush.h
File Facts
- System
- Linux kernel
- Corpus path
arch/xtensa/include/asm/tlbflush.h- Extension
.h- Size
- 5622 bytes
- Lines
- 206
- Domain
- Architecture Layer
- Bucket
- arch/xtensa
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/stringify.hasm/processor.h
Detected Declarations
function itlb_probefunction dtlb_probefunction invalidate_itlb_entryfunction invalidate_dtlb_entryfunction invalidate_itlb_entry_no_isyncfunction invalidate_dtlb_entry_no_isyncfunction set_itlbcfg_registerfunction set_dtlbcfg_registerfunction set_ptevaddr_registerfunction read_ptevaddr_registerfunction write_dtlb_entryfunction write_itlb_entryfunction invalidate_page_directoryfunction invalidate_itlb_mappingfunction invalidate_dtlb_mappingfunction read_dtlb_virtualfunction read_dtlb_translationfunction read_itlb_virtualfunction read_itlb_translation
Annotated Snippet
#ifndef _XTENSA_TLBFLUSH_H
#define _XTENSA_TLBFLUSH_H
#include <linux/stringify.h>
#include <asm/processor.h>
#define DTLB_WAY_PGD 7
#define ITLB_ARF_WAYS 4
#define DTLB_ARF_WAYS 4
#define ITLB_HIT_BIT 3
#define DTLB_HIT_BIT 4
#ifndef __ASSEMBLER__
/* TLB flushing:
*
* - flush_tlb_all() flushes all processes TLB entries
* - flush_tlb_mm(mm) flushes the specified mm context TLB entries
* - flush_tlb_page(vma, page) flushes a single page
* - flush_tlb_range(vma, vmaddr, end) flushes a range of pages
*/
void local_flush_tlb_all(void);
void local_flush_tlb_mm(struct mm_struct *mm);
void local_flush_tlb_page(struct vm_area_struct *vma,
unsigned long page);
void local_flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end);
#ifdef CONFIG_SMP
void flush_tlb_all(void);
void flush_tlb_mm(struct mm_struct *);
void flush_tlb_page(struct vm_area_struct *, unsigned long);
void flush_tlb_range(struct vm_area_struct *, unsigned long,
unsigned long);
void flush_tlb_kernel_range(unsigned long start, unsigned long end);
#else /* !CONFIG_SMP */
#define flush_tlb_all() local_flush_tlb_all()
#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, \
end)
#define flush_tlb_kernel_range(start, end) local_flush_tlb_kernel_range(start, \
end)
#endif /* CONFIG_SMP */
/* TLB operations. */
static inline unsigned long itlb_probe(unsigned long addr)
{
unsigned long tmp;
__asm__ __volatile__("pitlb %0, %1\n\t" : "=a" (tmp) : "a" (addr));
return tmp;
}
static inline unsigned long dtlb_probe(unsigned long addr)
{
unsigned long tmp;
__asm__ __volatile__("pdtlb %0, %1\n\t" : "=a" (tmp) : "a" (addr));
return tmp;
}
static inline void invalidate_itlb_entry (unsigned long probe)
{
__asm__ __volatile__("iitlb %0; isync\n\t" : : "a" (probe));
}
static inline void invalidate_dtlb_entry (unsigned long probe)
{
__asm__ __volatile__("idtlb %0; dsync\n\t" : : "a" (probe));
}
/* Use the .._no_isync functions with caution. Generally, these are
* handy for bulk invalidates followed by a single 'isync'. The
* caller must follow up with an 'isync', which can be relatively
* expensive on some Xtensa implementations.
*/
static inline void invalidate_itlb_entry_no_isync (unsigned entry)
{
/* Caller must follow up with 'isync'. */
__asm__ __volatile__ ("iitlb %0\n" : : "a" (entry) );
}
Annotation
- Immediate include surface: `linux/stringify.h`, `asm/processor.h`.
- Detected declarations: `function itlb_probe`, `function dtlb_probe`, `function invalidate_itlb_entry`, `function invalidate_dtlb_entry`, `function invalidate_itlb_entry_no_isync`, `function invalidate_dtlb_entry_no_isync`, `function set_itlbcfg_register`, `function set_dtlbcfg_register`, `function set_ptevaddr_register`, `function read_ptevaddr_register`.
- Atlas domain: Architecture Layer / arch/xtensa.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.