arch/xtensa/kernel/entry.S

Source file repositories/reference/linux-study-clean/arch/xtensa/kernel/entry.S

File Facts

System
Linux kernel
Corpus path
arch/xtensa/kernel/entry.S
Extension
.S
Size
54109 bytes
Lines
2265
Domain
Architecture Layer
Bucket
arch/xtensa
Inferred role
Architecture Layer: arch/xtensa
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

* We can get here with NMI in the middle of context_switch that
	 * touches vmalloc area.
	 */
	movi	a0, init_mm
	j	.Lfast_second_level_miss_continue

.Lfast_second_level_miss_no_pmd:
#if (DCACHE_WAY_SIZE > PAGE_SIZE)

	/* Special case for cache aliasing.
	 * We (should) only get here if a clear_user_page, copy_user_page
	 * or the aliased cache flush functions got preemptively interrupted 
	 * by another task. Re-establish temporary mapping to the 
	 * TLBTEMP_BASE areas.
	 */

	/* We shouldn't be in a double exception */

	l32i	a0, a2, PT_DEPC
	bgeui	a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lfast_second_level_miss_slow

	/* Make sure the exception originated in the special functions */

	movi	a0, __tlbtemp_mapping_start
	rsr	a3, epc1
	bltu	a3, a0, .Lfast_second_level_miss_slow
	movi	a0, __tlbtemp_mapping_end
	bgeu	a3, a0, .Lfast_second_level_miss_slow

	/* Check if excvaddr was in one of the TLBTEMP_BASE areas. */

	movi	a3, TLBTEMP_BASE_1
	rsr	a0, excvaddr
	bltu	a0, a3, .Lfast_second_level_miss_slow

	addi	a1, a0, -TLBTEMP_SIZE
	bgeu	a1, a3, .Lfast_second_level_miss_slow

	/* Check if we have to restore an ITLB mapping. */

	movi	a1, __tlbtemp_mapping_itlb
	rsr	a3, epc1
	sub	a3, a3, a1

	/* Calculate VPN */

	movi	a1, PAGE_MASK
	and	a1, a1, a0

	/* Jump for ITLB entry */

	bgez	a3, 1f

	/* We can use up to two TLBTEMP areas, one for src and one for dst. */

	extui	a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
	add	a1, a3, a1

	/* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */

	mov	a0, a6
	movnez	a0, a7, a3
	j	.Lfast_second_level_miss_wdtlb

	/* ITLB entry. We only use dst in a6. */

1:	witlb	a6, a1
	isync
	j	.Lfast_second_level_miss_skip_wdtlb

Annotation

Implementation Notes