arch/xtensa/kernel/head.S

Source file repositories/reference/linux-study-clean/arch/xtensa/kernel/head.S

File Facts

System
Linux kernel
Corpus path
arch/xtensa/kernel/head.S
Extension
.S
Size
7092 bytes
Lines
384
Domain
Architecture Layer
Bucket
arch/xtensa
Inferred role
Architecture Layer: arch/xtensa
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

abi_call	start_kernel

should_never_return:
	j	should_never_return

#ifdef CONFIG_SMP
.Lboot_secondary:

	movi	a2, cpu_start_ccount
1:
	memw
	l32i	a3, a2, 0
	beqi	a3, 0, 1b
	movi	a3, 0
	s32i	a3, a2, 0
1:
	memw
	l32i	a3, a2, 0
	beqi	a3, 0, 1b
	wsr	a3, ccount
	movi	a3, 0
	s32i	a3, a2, 0
	memw

	movi	abi_arg0, 0
	wsr	abi_arg0, excsave1

	abi_call	secondary_start_kernel
	j	should_never_return

#endif  /* CONFIG_SMP */

ENDPROC(_startup)

#ifdef CONFIG_HOTPLUG_CPU

ENTRY(cpu_restart)

#if XCHAL_DCACHE_IS_WRITEBACK
	___flush_invalidate_dcache_all a2 a3
#else
	___invalidate_dcache_all a2 a3
#endif
	memw
	movi	a2, CCON	# MX External Register to Configure Cache
	movi	a3, 0
	wer	a3, a2
	extw

	rsr	a0, prid
	neg	a2, a0
	movi	a3, cpu_start_id
	memw
	s32i	a2, a3, 0
#if XCHAL_DCACHE_IS_WRITEBACK
	dhwbi	a3, 0
#endif
1:
	memw
	l32i	a2, a3, 0
	dhi	a3, 0
	bne	a2, a0, 1b

	/*
	 * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
	 * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
	 * xt-gdb to single step via DEBUG exceptions received directly
	 * by ocd.
	 */
	movi	a1, 1

Annotation

Implementation Notes