arch/xtensa/kernel/xtensa_ksyms.c
Source file repositories/reference/linux-study-clean/arch/xtensa/kernel/xtensa_ksyms.c
File Facts
- System
- Linux kernel
- Corpus path
arch/xtensa/kernel/xtensa_ksyms.c- Extension
.c- Size
- 660 bytes
- Lines
- 29
- Domain
- Architecture Layer
- Bucket
- arch/xtensa
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
Dependency Surface
linux/module.hasm/pgtable.h
Detected Declarations
function Copyrightfunction __sync_fetch_and_or_4export __sync_fetch_and_and_4export __sync_fetch_and_or_4
Annotated Snippet
#include <linux/module.h>
#include <asm/pgtable.h>
unsigned int __sync_fetch_and_and_4(volatile void *p, unsigned int v)
{
BUG();
}
EXPORT_SYMBOL(__sync_fetch_and_and_4);
unsigned int __sync_fetch_and_or_4(volatile void *p, unsigned int v)
{
BUG();
}
EXPORT_SYMBOL(__sync_fetch_and_or_4);
Annotation
- Immediate include surface: `linux/module.h`, `asm/pgtable.h`.
- Detected declarations: `function Copyright`, `function __sync_fetch_and_or_4`, `export __sync_fetch_and_and_4`, `export __sync_fetch_and_or_4`.
- Atlas domain: Architecture Layer / arch/xtensa.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.