arch/xtensa/mm/cache.c
Source file repositories/reference/linux-study-clean/arch/xtensa/mm/cache.c
File Facts
- System
- Linux kernel
- Corpus path
arch/xtensa/mm/cache.c- Extension
.c- Size
- 8862 bytes
- Lines
- 336
- Domain
- Architecture Layer
- Bucket
- arch/xtensa
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/signal.hlinux/sched.hlinux/kernel.hlinux/errno.hlinux/string.hlinux/types.hlinux/ptrace.hlinux/memblock.hlinux/swap.hlinux/pagemap.hlinux/pgtable.hasm/bootparam.hasm/mmu_context.hasm/tlb.hasm/tlbflush.hasm/page.h
Detected Declarations
function Copyrightfunction clear_user_highpagefunction copy_user_highpagefunction flush_dcache_foliofunction update_mmufunction local_flush_cache_rangefunction local_flush_cache_pagefunction update_mmu_cache_rangefunction access_process_vmfunction copy_from_user_pageexport clear_user_highpageexport copy_user_highpageexport flush_dcache_folioexport local_flush_cache_rangeexport local_flush_cache_page
Annotated Snippet
if (!PageHighMem(page)) {
kvaddr = (unsigned long)page_to_virt(page);
__invalidate_dcache_page(kvaddr);
} else {
kvaddr = TLBTEMP_BASE_1 +
(page_to_phys(page) & DCACHE_ALIAS_MASK);
preempt_disable();
__invalidate_dcache_page_alias(kvaddr,
page_to_phys(page));
preempt_enable();
}
}
}
static inline void *coherent_kvaddr(struct page *page, unsigned long base,
unsigned long vaddr, unsigned long *paddr)
{
*paddr = page_to_phys(page);
return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
}
void clear_user_highpage(struct page *page, unsigned long vaddr)
{
struct folio *folio = page_folio(page);
unsigned long paddr;
void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
preempt_disable();
kmap_invalidate_coherent(page, vaddr);
set_bit(PG_arch_1, folio_flags(folio, 0));
clear_page_alias(kvaddr, paddr);
preempt_enable();
}
EXPORT_SYMBOL(clear_user_highpage);
void copy_user_highpage(struct page *dst, struct page *src,
unsigned long vaddr, struct vm_area_struct *vma)
{
struct folio *folio = page_folio(dst);
unsigned long dst_paddr, src_paddr;
void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
&dst_paddr);
void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
&src_paddr);
preempt_disable();
kmap_invalidate_coherent(dst, vaddr);
set_bit(PG_arch_1, folio_flags(folio, 0));
copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
preempt_enable();
}
EXPORT_SYMBOL(copy_user_highpage);
/*
* Any time the kernel writes to a user page cache page, or it is about to
* read from a page cache page this routine is called.
*
*/
void flush_dcache_folio(struct folio *folio)
{
struct address_space *mapping = folio_flush_mapping(folio);
/*
* If we have a mapping but the page is not mapped to user-space
* yet, we simply mark this page dirty and defer flushing the
* caches until update_mmu().
*/
if (mapping && !mapping_mapped(mapping)) {
if (!test_bit(PG_arch_1, &folio->flags.f))
set_bit(PG_arch_1, &folio->flags.f);
return;
} else {
unsigned long phys = folio_pfn(folio) * PAGE_SIZE;
unsigned long temp = folio_pos(folio);
unsigned int i, nr = folio_nr_pages(folio);
unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
unsigned long virt;
/*
* Flush the page in kernel space and user space.
* Note that we can omit that step if aliasing is not
* an issue, but we do have to synchronize I$ and D$
* if we have a mapping.
*/
Annotation
- Immediate include surface: `linux/init.h`, `linux/signal.h`, `linux/sched.h`, `linux/kernel.h`, `linux/errno.h`, `linux/string.h`, `linux/types.h`, `linux/ptrace.h`.
- Detected declarations: `function Copyright`, `function clear_user_highpage`, `function copy_user_highpage`, `function flush_dcache_folio`, `function update_mmu`, `function local_flush_cache_range`, `function local_flush_cache_page`, `function update_mmu_cache_range`, `function access_process_vm`, `function copy_from_user_page`.
- Atlas domain: Architecture Layer / arch/xtensa.
- Implementation status: integration implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.