Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
Source file repositories/reference/linux-study-clean/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
File Facts
- System
- Linux kernel
- Corpus path
Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache- Extension
[no extension]- Size
- 506 bytes
- Lines
- 13
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: Documentation
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
What: /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode
Date: November 2024
KernelVersion: 6.13
Contact: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Description: (RW) AMD 3D V-Cache optimizer allows users to switch CPU core
rankings dynamically.
This file switches between these two modes:
- "frequency" cores within the faster CCD are prioritized before
those in the slower CCD.
- "cache" cores within the larger L3 CCD are prioritized before
those in the smaller L3 CCD.Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.