Documentation/arch/arm64/sve.rst

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===================================================
Scalable Vector Extension support for AArch64 Linux
===================================================

Author: Dave Martin <Dave.Martin@arm.com>

Date:   4 August 2017

This document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Scalable Vector Extension (SVE), including
interactions with Streaming SVE mode added by the Scalable Matrix Extension
(SME).

This is an outline of the most important features and issues only and not
intended to be exhaustive.

This document does not aim to describe the SVE architecture or programmer's
model.  To aid understanding, a minimal description of relevant programmer's
model features for SVE is included in Appendix A.


1.  General
-----------

* SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
  tracked per-thread.

* In streaming mode FFR is not accessible unless HWCAP2_SME_FA64 is present
  in the system, when it is not supported and these interfaces are used to
  access streaming mode FFR is read and written as zero.

* The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
  AT_HWCAP entry.  Presence of this flag implies the presence of the SVE
  instructions and registers, and the Linux-specific system interfaces
  described in this document.  SVE is reported in /proc/cpuinfo as "sve".

* Support for the execution of SVE instructions in userspace can also be
  detected by reading the CPU ID register ID_AA64PFR0_EL1 using an MRS
  instruction, and checking that the value of the SVE field is nonzero. [3]

  It does not guarantee the presence of the system interfaces described in the
  following sections: software that needs to verify that those interfaces are
  present must check for HWCAP_SVE instead.

* On hardware that supports the SVE2 extensions, HWCAP2_SVE2 will also
  be reported in the AT_HWCAP2 aux vector entry.  In addition to this,
  optional extensions to SVE2 may be reported by the presence of:

	HWCAP2_SVE2
	HWCAP2_SVEAES
	HWCAP2_SVEPMULL
	HWCAP2_SVEBITPERM
	HWCAP2_SVESHA3
	HWCAP2_SVESM4
	HWCAP2_SVE2P1

  This list may be extended over time as the SVE architecture evolves.

  These extensions are also reported via the CPU ID register ID_AA64ZFR0_EL1,
  which userspace can read using an MRS instruction.  See elf_hwcaps.txt and
  cpu-feature-registers.txt for details.

* On hardware that supports the SME extensions, HWCAP2_SME will also be
  reported in the AT_HWCAP2 aux vector entry.  Among other things SME adds
  streaming mode which provides a subset of the SVE feature set using a
  separate SME vector length and the same Z/V registers.  See sme.rst
  for more details.

* Debuggers should restrict themselves to interacting with the target via the
  NT_ARM_SVE regset.  The recommended way of detecting support for this regset

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