Documentation/arch/x86/amd-hfi.rst

Source file repositories/reference/linux-study-clean/Documentation/arch/x86/amd-hfi.rst

File Facts

System
Linux kernel
Corpus path
Documentation/arch/x86/amd-hfi.rst
Extension
.rst
Size
6899 bytes
Lines
134
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: documentation
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

.. SPDX-License-Identifier: GPL-2.0

======================================================================
Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform
======================================================================

:Copyright: 2025 Advanced Micro Devices, Inc. All Rights Reserved.

:Author: Perry Yuan <perry.yuan@amd.com>
:Author: Mario Limonciello <mario.limonciello@amd.com>

Overview
--------

AMD Heterogeneous Core implementations are comprised of more than one
architectural class and CPUs are comprised of cores of various efficiency and
power capabilities: performance-oriented *classic cores* and power-efficient
*dense cores*. As such, power management strategies must be designed to
accommodate the complexities introduced by incorporating different core types.
Heterogeneous systems can also extend to more than two architectural classes
as well. The purpose of the scheduling feedback mechanism is to provide
information to the operating system scheduler in real time such that the
scheduler can direct threads to the optimal core.

The goal of AMD's heterogeneous architecture is to attain power benefit by
sending background threads to the dense cores while sending high priority
threads to the classic cores. From a performance perspective, sending
background threads to dense cores can free up power headroom and allow the
classic cores to optimally service demanding threads. Furthermore, the area
optimized nature of the dense cores allows for an increasing number of
physical cores. This improved core density will have positive multithreaded
performance impact.

AMD Heterogeneous Core Driver
-----------------------------

The ``amd_hfi`` driver delivers the operating system a performance and energy
efficiency capability data for each CPU in the system. The scheduler can use
the ranking data from the HFI driver to make task placement decisions.

Thread Classification and Ranking Table Interaction
----------------------------------------------------

The thread classification is used to select into a ranking table that
describes an efficiency and performance ranking for each classification.

Threads are classified during runtime into enumerated classes. The classes
represent thread performance/power characteristics that may benefit from
special scheduling behaviors. The below table depicts an example of thread
classification and a preference where a given thread should be scheduled
based on its thread class. The real time thread classification is consumed
by the operating system and is used to inform the scheduler of where the
thread should be placed.

Thread Classification Example Table
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+----------+----------------+-------------------------------+---------------------+---------+
| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter |
+----------+----------------+-------------------------------+---------------------+---------+
| 0        | Default        | Performant                    | Highest             |         |
+----------+----------------+-------------------------------+---------------------+---------+
| 1        | Non-scalable   | Efficient                     | Lowest              | PMCx1A1 |
+----------+----------------+-------------------------------+---------------------+---------+
| 2        | I/O bound      | Efficient                     | Lowest              | PMCx044 |
+----------+----------------+-------------------------------+---------------------+---------+

Thread classification is performed by the hardware each time that the thread is switched out.
Threads that don't meet any hardware specified criteria are classified as "default".

AMD Hardware Feedback Interface

Annotation

Implementation Notes