Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
Extension
.yaml
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9851 bytes
Lines
248
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Express and Juno Boards

maintainers:
  - Sudeep Holla <sudeep.holla@arm.com>
  - Linus Walleij <linusw@kernel.org>

description: |+
  ARM's Versatile Express platform were built as reference designs for exploring
  multicore Cortex-A class systems. The Versatile Express family contains both
  32 bit (Aarch32) and 64 bit (Aarch64) systems.

  The board consist of a motherboard and one or more daughterboards (tiles). The
  motherboard provides a set of peripherals. Processor and RAM "live" on the
  tiles.

  The motherboard and each core tile should be described by a separate Device
  Tree source file, with the tile's description including the motherboard file
  using an include directive. As the motherboard can be initialized in one of
  two different configurations ("memory maps"), care must be taken to include
  the correct one.

  When a new generation of boards were introduced under the name "Juno", these
  shared to many common characteristics with the Versatile Express that the
  "arm,vexpress" compatible was retained in the root node, and these are
  included in this binding schema as well.

  The root node indicates the CPU SoC on the core tile, and this
  is a daughterboard to the main motherboard. The name used in the compatible
  string shall match the name given in the core tile's technical reference
  manual, followed by "arm,vexpress" as an additional compatible value. If
  further subvariants are released of the core tile, even more fine-granular
  compatible strings with up to three compatible strings are used.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
          in MPCore configuration in a test chip on the core tile. See ARM
          DUI 0448I. This was the first Versatile Express platform.
        items:
          - const: arm,vexpress,v2p-ca9
          - const: arm,vexpress
      - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
          in a test chip on the core tile. It is intended to evaluate NEON, FPU
          and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
        items:
          - const: arm,vexpress,v2p-ca5s
          - const: arm,vexpress
      - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
          cores in a MPCore configuration in a test chip on the core tile. See
          ARM DUI 0604F.
        items:
          - const: arm,vexpress,v2p-ca15
          - const: arm,vexpress
      - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
          A15 CPU cores in a test chip on the core tile. This is the first test
          chip called "TC1".
        items:
          - const: arm,vexpress,v2p-ca15,tc1
          - const: arm,vexpress,v2p-ca15
          - const: arm,vexpress
      - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15

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