Documentation/devicetree/bindings/arm/cpus.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/arm/cpus.yaml

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Linux kernel
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Documentation/devicetree/bindings/arm/cpus.yaml
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.yaml
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM CPUs

maintainers:
  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

description: |+
  The device tree allows to describe the layout of CPUs in a system through the
  "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining
  properties for every cpu.

  Bindings for CPU nodes follow the Devicetree Specification, available from:

  https://www.devicetree.org/specifications/

  with updates for 32-bit and 64-bit ARM systems provided in this document.

  ================================
  Convention used in this document
  ================================

  This document follows the conventions described in the Devicetree
  Specification, with the addition:

  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
    the reg property contained in bits 7 down to 0

  =====================================
  cpus and cpu node bindings definition
  =====================================

  The ARM architecture, in accordance with the Devicetree Specification,
  requires the cpus and cpu nodes to be present and contain the properties
  described below.

properties:
  reg:
    maxItems: 1
    description: >
      Usage and definition depend on ARM architecture version and configuration:

      On uniprocessor ARM architectures previous to v7 this property is required
      and must be set to 0.

      On ARM 11 MPcore based systems this property is required and matches the
      CPUID[11:0] register bits.

        Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register.

        All other bits in the reg cell must be set to 0.

      On 32-bit ARM v7 or later systems this property is required and matches
      the CPU MPIDR[23:0] register bits.

        Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR.

        All other bits in the reg cell must be set to 0.

      On ARM v8 64-bit systems this property is required and matches the
      MPIDR_EL1 register affinity bits.

        * If cpus node's #address-cells property is set to 2

          The first reg cell bits [7:0] must be set to bits [39:32] of
          MPIDR_EL1.

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