Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
Extension
.yaml
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3766 bytes
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169
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner Memory Bus (MBUS) controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The MBUS controller drives the MBUS that other devices in the SoC
  will use to perform DMA. It also has a register interface that
  allows to monitor and control the bandwidth and priorities for
  masters on that bus.

  Each device having to perform their DMA through the MBUS must have
  the interconnects and interconnect-names properties set to the MBUS
  controller and with "dma-mem" as the interconnect name.

properties:
  "#interconnect-cells":
    const: 1
    description:
      The content of the cell is the MBUS ID.

  compatible:
    enum:
      - allwinner,sun5i-a13-mbus
      - allwinner,sun8i-a33-mbus
      - allwinner,sun8i-a50-mbus
      - allwinner,sun8i-a83t-mbus
      - allwinner,sun8i-h3-mbus
      - allwinner,sun8i-r40-mbus
      - allwinner,sun8i-v3s-mbus
      - allwinner,sun8i-v536-mbus
      - allwinner,sun20i-d1-mbus
      - allwinner,sun50i-a64-mbus
      - allwinner,sun50i-a100-mbus
      - allwinner,sun50i-h5-mbus
      - allwinner,sun50i-h6-mbus
      - allwinner,sun50i-h616-mbus
      - allwinner,sun50i-r329-mbus

  reg:
    minItems: 1
    items:
      - description: MBUS interconnect/bandwidth limit/PMU registers
      - description: DRAM controller/PHY registers

  reg-names:
    minItems: 1
    items:
      - const: mbus
      - const: dram

  clocks:
    minItems: 1
    items:
      - description: MBUS interconnect module clock
      - description: DRAM controller/PHY module clock
      - description: Register bus clock, shared by MBUS and DRAM

  clock-names:
    minItems: 1
    items:
      - const: mbus
      - const: dram

Annotation

Implementation Notes