Documentation/devicetree/bindings/ata/sata_highbank.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/ata/sata_highbank.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/ata/sata_highbank.yaml- Extension
.yaml- Size
- 2572 bytes
- Lines
- 96
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda AHCI SATA Controller
description: |
The Calxeda SATA controller mostly conforms to the AHCI interface
with some special extensions to add functionality, to map GPIOs for
activity LEDs and for mapping the ComboPHYs.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: calxeda,hb-ahci
reg:
maxItems: 1
interrupts:
maxItems: 1
dma-coherent: true
calxeda,pre-clocks:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Indicates the number of additional clock cycles to transmit before
sending an SGPIO pattern.
calxeda,post-clocks:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Indicates the number of additional clock cycles to transmit after
sending an SGPIO pattern.
calxeda,led-order:
description: Maps port numbers to offsets within the SGPIO bitstream.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
calxeda,port-phys:
description: |
phandle-combophy and lane assignment, which maps each SATA port to a
combophy and a lane within that combophy
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
items:
maxItems: 2
calxeda,tx-atten:
description: |
Contains TX attenuation override codes, one per port.
The upper 24 bits of each entry are always 0 and thus ignored.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
calxeda,sgpio-gpio:
maxItems: 3
description: |
phandle-gpio bank, bit offset, and default on or off, which indicates
that the driver supports SGPIO indicator lights using the indicated
GPIOs.
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.