Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
Extension
.yaml
Size
2671 bytes
Lines
107
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC AHCI SATA controller properties

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  This document defines device tree schema for the generic Synopsys DWC
  AHCI controller properties.

select: false

allOf:
  - $ref: ahci-common.yaml#

properties:
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description:
      Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
      PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
      clock, etc.
    minItems: 1
    maxItems: 6

  clock-names:
    minItems: 1
    maxItems: 6
    items:
      oneOf:
        - description: Application APB/AHB/AXI BIU clock
          enum:
            - pclk
            - aclk
            - hclk
            - sata
        - description: Power Module keep-alive clock
          const: pmalive
        - description: RxOOB detection clock
          const: rxoob
        - description: PHY Transmit Clock
          const: asic
        - description: PHY Receive Clock
          const: rbc
        - description: SATA Ports reference clock
          const: ref

  resets:
    description:
      At least basic application and reference clock domains resets are
      normally supported by the DWC AHCI SATA controller.
    minItems: 1
    maxItems: 4

  reset-names:
    minItems: 1
    maxItems: 4
    items:
      oneOf:
        - description: Application AHB/AXI BIU clock domain reset control

Annotation

Implementation Notes