Documentation/devicetree/bindings/cache/l2c2x0.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/cache/l2c2x0.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/cache/l2c2x0.yaml
Extension
.yaml
Size
7895 bytes
Lines
245
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM L2 Cache Controller

maintainers:
  - Rob Herring <robh@kernel.org>

description: |+
  ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
  PL220/PL310 and variants) based level 2 cache controller. All these various
  implementations of the L2 cache controller have compatible programming
  models (Note 1). Some of the properties that are just prefixed "cache-*" are
  taken from section 3.7.3 of the Devicetree Specification which can be found
  at:
  https://www.devicetree.org/specifications/

  Note 1: The description in this document doesn't apply to integrated L2
    cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
    integrated L2 controllers are assumed to be all preconfigured by
    early secure boot code. Thus no need to deal with their configuration
    in the kernel at all.

allOf:
  - $ref: /schemas/cache-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - arm,pl310-cache
          - arm,l220-cache
          - arm,l210-cache
            # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
          - bcm,bcm11351-a2-pl310-cache
            # For Broadcom bcm11351 chipset where an
            # offset needs to be added to the address before passing down to the L2
            # cache controller
          - brcm,bcm11351-a2-pl310-cache
            # Marvell Controller designed to be
            # compatible with the ARM one, with system cache mode (meaning
            # maintenance operations on L1 are broadcasted to the L2 and L2
            # performs the same operation).
          - marvell,aurora-system-cache
            # Marvell Controller designed to be
            # compatible with the ARM one with outer cache mode.
          - marvell,aurora-outer-cache
      - items:
           # Marvell Tauros3 cache controller, compatible
           # with arm,pl310-cache controller.
          - const: marvell,tauros3-cache
          - const: arm,pl310-cache

  cache-level:
    const: 2

  cache-unified: true
  cache-size: true
  cache-sets: true
  cache-block-size: true
  cache-line-size: true

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

Annotation

Implementation Notes