Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
Extension
.yaml
Size
1725 bytes
Lines
73
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices AXI clkgen pcore clock generator

maintainers:
  - Lars-Peter Clausen <lars@metafoo.de>
  - Michael Hennerich <michael.hennerich@analog.com>

description: |
  The axi_clkgen IP core is a software programmable clock generator,
  that can be synthesized on various FPGA platforms.

  Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen

properties:
  compatible:
    enum:
      - adi,axi-clkgen-2.00.a
      - adi,zynqmp-axi-clkgen-2.00.a

  clocks:
    description:
      Specifies the reference clock(s) from which the output frequency is
      derived. This must either reference one clock if only the first clock
      input is connected or two if both clock inputs are connected. The last
      clock is the AXI bus clock that needs to be enabled so we can access the
      core registers.
    minItems: 2
    maxItems: 3

  clock-names:
    oneOf:
      - items:
          - const: clkin1
          - const: s_axi_aclk
      - items:
          - const: clkin1
          - const: clkin2
          - const: s_axi_aclk

  clock-output-names:
    maxItems: 1

  '#clock-cells':
    const: 0

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@ff000000 {
      compatible = "adi,axi-clkgen-2.00.a";
      #clock-cells = <0>;
      reg = <0xff000000 0x1000>;
      clocks = <&osc 1>, <&clkc 15>;
      clock-names = "clkin1", "s_axi_aclk";

Annotation

Implementation Notes