Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml
Extension
.yaml
Size
6617 bytes
Lines
202
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic AXG Audio Clock Controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>
  - Jerome Brunet <jbrunet@baylibre.com>

description:
  The Amlogic AXG audio clock controller generates and supplies clock to the
  other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
  devices.

properties:
  compatible:
    enum:
      - amlogic,axg-audio-clkc
      - amlogic,g12a-audio-clkc
      - amlogic,sm1-audio-clkc

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: main peripheral bus clock
      - description: input plls to generate clock signals N0
      - description: input plls to generate clock signals N1
      - description: input plls to generate clock signals N2
      - description: input plls to generate clock signals N3
      - description: input plls to generate clock signals N4
      - description: input plls to generate clock signals N5
      - description: input plls to generate clock signals N6
      - description: input plls to generate clock signals N7
      - description: slave bit clock N0 provided by external components
      - description: slave bit clock N1 provided by external components
      - description: slave bit clock N2 provided by external components
      - description: slave bit clock N3 provided by external components
      - description: slave bit clock N4 provided by external components
      - description: slave bit clock N5 provided by external components
      - description: slave bit clock N6 provided by external components
      - description: slave bit clock N7 provided by external components
      - description: slave bit clock N8 provided by external components
      - description: slave bit clock N9 provided by external components
      - description: slave sample clock N0 provided by external components
      - description: slave sample clock N1 provided by external components
      - description: slave sample clock N2 provided by external components
      - description: slave sample clock N3 provided by external components
      - description: slave sample clock N4 provided by external components
      - description: slave sample clock N5 provided by external components
      - description: slave sample clock N6 provided by external components
      - description: slave sample clock N7 provided by external components
      - description: slave sample clock N8 provided by external components
      - description: slave sample clock N9 provided by external components

  clock-names:
    minItems: 1
    items:
      - const: pclk

Annotation

Implementation Notes