Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml
Extension
.yaml
Size
13896 bytes
Lines
418
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom iProc Family Clocks

maintainers:
  - Ray Jui <rjui@broadcom.com>
  - Scott Branden <sbranden@broadcom.com>

description: |
  The iProc clock controller manages clocks that are common to the iProc family.
  An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
  LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
  comprises of several leaf clocks

  ASIU clocks are a special case. These clocks are derived directly from the
  reference clock of the onboard crystal.

properties:
  compatible:
    enum:
      - brcm,bcm63138-armpll
      - brcm,cygnus-armpll
      - brcm,cygnus-genpll
      - brcm,cygnus-lcpll0
      - brcm,cygnus-mipipll
      - brcm,cygnus-asiu-clk
      - brcm,cygnus-audiopll
      - brcm,hr2-armpll
      - brcm,nsp-armpll
      - brcm,nsp-genpll
      - brcm,nsp-lcpll0
      - brcm,ns2-genpll-scr
      - brcm,ns2-genpll-sw
      - brcm,ns2-lcpll-ddr
      - brcm,ns2-lcpll-ports
      - brcm,sr-genpll0
      - brcm,sr-genpll1
      - brcm,sr-genpll2
      - brcm,sr-genpll3
      - brcm,sr-genpll4
      - brcm,sr-genpll5
      - brcm,sr-genpll6
      - brcm,sr-lcpll0
      - brcm,sr-lcpll1
      - brcm,sr-lcpll-pcie

  reg:
    minItems: 1
    items:
      - description: base register
      - description: power register
      - description: ASIU or split status register

  clocks:
    description: The input parent clock phandle for the PLL / ASIU clock. For
      most iProc PLLs, this is an onboard crystal with a fixed rate.
    maxItems: 1

  '#clock-cells':
    true

  clock-output-names:
    minItems: 1
    maxItems: 45

allOf:

Annotation

Implementation Notes